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    Three-dimensional memory device and fabrication method thereof
    2.
    发明授权
    Three-dimensional memory device and fabrication method thereof 有权

    公开(公告)号：US11410983B2

    公开(公告)日：2022-08-09

    申请号：US17115002

    申请日：2020-12-08

    申请人： Yangtze Memory Technologies Co., Ltd.

    发明人： Ziqi Chen ,  Chao Li ,  Guanping Wu

    IPC分类号： H01L27/11575 ,  H01L25/00 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/00 ,  H01L25/065

    摘要： Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed memory device comprises multiple staircase structures stacked over a substrate. The multiple staircase structures are positioned in a dielectric fill structure over the substrate. Each staircase structure comprises multiple gate electrodes separated by multiple insulating layers. The memory device further comprises a semiconductor channel extending from through the multiple staircase structures into the substrate. A first portion of peripheral via structures extends through the dielectric fill structure and is connected to the gate electrodes of each staircase structure. A second portion of peripheral via structures extend through the dielectric fill structure and is connected to a peripheral device over the substrate and neighboring staircase structures.

    JOINT OPENING STRUCTURES OF THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME
    7.
    发明申请
    JOINT OPENING STRUCTURES OF THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME 有权

    公开(公告)号：US20230016627A1

    公开(公告)日：2023-01-19

    申请号：US17934161

    申请日：2022-09-21

    申请人： Yangtze Memory Technologies Co., Ltd.

    发明人： Zhenyu LU ,  Wenguang Shi ,  Guanping Wu ,  Feng Pan ,  Xianjin Wan ,  Baoyou Chen

    IPC分类号： H01L27/11578 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

    摘要： Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.

    THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATION METHOD THEREOF
    8.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20210118867A1

    公开(公告)日：2021-04-22

    申请号：US17115143

    申请日：2020-12-08

    申请人： Yangtze Memory Technologies Co., Ltd.

    发明人： Ziqi CHEN ,  Chao Li ,  Guanping Wu

    IPC分类号： H01L25/00 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/00 ,  H01L25/065

    摘要： Methods and structures of a three-dimensional memory device are disclosed. In an example, the method for forming a memory device includes the following operations. First, a plurality of first semiconductor channels can be formed over a first wafer with a peripheral device and a plurality of first via structures neighboring the plurality of first semiconductor channels. The plurality of first semiconductor channels can extend along a direction perpendicular to a surface of the first wafer. Further, a plurality of second semiconductor channels can be formed over a second wafer with a plurality of second via structures neighboring the plurality of second semiconductor channels. The plurality of second semiconductor channels can extend along a direction perpendicular to a surface of the second wafer and a peripheral via structure.

    Joint opening structures of three-dimensional memory devices and methods for forming the same
    9.
    发明授权
    Joint opening structures of three-dimensional memory devices and methods for forming the same 有权

    公开(公告)号：US10886291B2

    公开(公告)日：2021-01-05

    申请号：US16046847

    申请日：2018-07-26

    申请人： Yangtze Memory Technologies Co., Ltd.

    发明人： Zhenyu Lu ,  Wenguang Shi ,  Guanping Wu ,  Feng Pan ,  Xianjin Wan ,  Baoyou Chen

    IPC分类号： H01L21/00 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565

    摘要： Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.

    Three-dimensional memory device and fabricating method thereof
    10.
    发明授权
    Three-dimensional memory device and fabricating method thereof 有权

    公开(公告)号：US10797067B2

    公开(公告)日：2020-10-06

    申请号：US16046679

    申请日：2018-07-26

    申请人： Yangtze Memory Technologies Co., Ltd.

    发明人： Ziqi Chen ,  Guanping Wu

    IPC分类号： H01L27/11582 ,  H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/10 ,  H01L21/768 ,  H01L21/28 ,  H01L21/02

    摘要： Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The method comprises: forming a recess region in a substrate including multiple protruding islands; forming a gate dielectric layer to cover top surfaces and sidewalls of the multiple protruding islands and a top surface of the recess region of the substrate; forming an underlying sacrificial layer on the gate dielectric layer to surround the sidewalls of the multiple protruding islands; forming an alternating dielectric stack including multiple alternatively stacked insulating layers and sacrificial layers on the underlying sacrificial layer and the multiple protruding islands; forming multiple channel holes penetrating the alternating dielectric stack, each channel hole is located corresponding to one of the multiple protruding islands; and forming a memory layer in each channel hole, wherein a channel layer of the memory layer is electrically connected with a corresponding protruding island.