公开(公告)号：US10109559B2

公开(公告)日：2018-10-23

申请号：US14470159

申请日：2014-08-27

申请人： XINTEC INC.

发明人： Chia-Sheng Lin ,  Yen-Shih Ho ,  Tsang-Yu Liu

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L27/146 ,  H01L31/02 ,  H01L23/31

摘要： An electronic device package and fabrication method thereof is provided. First, a semiconductor substrate is provided and the upper surface of it is etched to from recesses. A first isolation layer is formed on the upper surface and the sidewalls of the recesses. A conductive part is formed to fulfill the recesses and a conductive pad is formed on the first isolation layer to connect the conductive part. An electronic device is combined with the semiconductor substrate on the supper surface, wherein the electronic device has a connecting pad electrically connected to the conductive pad. The semiconductor substrate is thinned form its lower surface to expose the conductive part. A second isolation layer is formed below the lower surface and has an opening to expose the conductive part. A redistribution metal line is formed below the second isolation layer and in the opening to electrically connect to the conductive part.

公开(公告)号：US20180175101A1

公开(公告)日：2018-06-21

申请号：US15848600

申请日：2017-12-20

申请人： XINTEC INC.

发明人： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chaung-Lin Lai

IPC分类号： H01L27/146 ,  H01L23/00 ,  H01L21/683

摘要： A method for manufacturing a semiconductor structure includes the following steps. A first carrier is adhered to a first surface of a wafer by a first temporary bonding layer. A second surface of the wafer facing away from the first carrier is etched to form at least one through hole and at least one trench, in which a conductive pad of the wafer is exposed through the through hole. An isolation layer is formed on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench. A second carrier is adhered to the second surface of the wafer by a second temporary bonding layer, and thus the through hole and the trench are covered by the second carrier. The first carrier and the first temporary bonding layer are removed.

公开(公告)号：US09881959B2

公开(公告)日：2018-01-30

申请号：US14819348

申请日：2015-08-05

申请人： XINTEC INC.

发明人： Po-Shen Lin ,  Chia-Sheng Lin ,  Yi-Ming Chang

IPC分类号： H01L27/146

CPC分类号： H01L27/14636 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687

摘要： A method of manufacturing chip package includes providing a semiconductor substrate having at least a photo diode and an interconnection layer. The interconnection layer is disposed on an upper surface of the semiconductor substrate and above the photo diode and electrically connected to the photo diode. At least a redistribution circuit is formed on the interconnection layer. The redistribution circuit is electrically connected to the interconnection layer. A packaging layer is formed on the redistribution circuit. Subsequently, a carrier substrate is attached to the packaging layer. A color filter is formed on a lower surface of the semiconductor substrate. A micro-lens module is formed under the color filter. The carrier substrate is removed.

公开(公告)号：US09711469B2

公开(公告)日：2017-07-18

申请号：US14715445

申请日：2015-05-18

申请人： XINTEC INC.

发明人： Geng-Peng Pan ,  Yi-Ming Chang ,  Chia-Sheng Lin

IPC分类号： H01L23/00 ,  H01L21/033 ,  H01L21/302 ,  H01L23/48 ,  H01L21/268 ,  H01L21/48 ,  H01L21/768

CPC分类号： H01L24/03 ,  H01L21/0273 ,  H01L21/0334 ,  H01L21/268 ,  H01L21/302 ,  H01L21/48 ,  H01L21/481 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03831 ,  H01L2224/05017 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2924/00014

摘要： A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad.

公开(公告)号：US09611143B2

公开(公告)日：2017-04-04

申请号：US14676738

申请日：2015-04-01

申请人： XINTEC INC.

发明人： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Yi-Ming Chang

IPC分类号： H01L21/00 ,  B81C1/00 ,  H01L21/78 ,  H01L23/00 ,  H01L21/683 ,  H01L27/146 ,  B81B7/00 ,  H01L23/544

CPC分类号： B81C1/00896 ,  B81B7/007 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L24/11 ,  H01L24/43 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/0231 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/05432 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for forming a chip package is provided. The method includes providing a substrate and a capping layer, wherein the substrate has a sensing device therein adjacent to a surface of the substrate. The capping layer is attached to the surface of the substrate by an adhesive layer, wherein the adhesive layer covers the sensing device. A dicing process is performed on the substrate, the adhesive layer, and the capping layer along a direction to form individual chip packages.

公开(公告)号：US09450015B2

公开(公告)日：2016-09-20

申请号：US15086809

申请日：2016-03-31

申请人： XINTEC INC.

发明人： Wei-Ming Chien ,  Chia-Sheng Lin ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC分类号： H01L27/146 ,  H01L21/768 ,  H01L33/62

CPC分类号： H01L27/14687 ,  H01L21/76898 ,  H01L27/14601 ,  H01L27/14636 ,  H01L33/62

摘要： A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.

摘要翻译： 半导体结构的制造方法包括以下步骤。 在晶片结构的晶片上形成图案化的光致抗蚀剂层。 蚀刻晶片，使得沟槽形成在晶片中，晶片结构的保护层通过沟道露出。 蚀刻保护层，使得在保护层中形成与沟道对准的开口。 保护层中的着陆垫分别通过开口和通道暴露，并且每个开口的口径朝着相应的通道逐渐增加。 蚀刻围绕通道的晶片的侧表面，使得通道膨胀以分别形成中空区域。 中空区域的口径朝向开口逐渐减小，并且开口的口径小于中空区域的口径。

公开(公告)号：US09196754B2

公开(公告)日：2015-11-24

申请号：US14516492

申请日：2014-10-16

申请人： XINTEC INC.

发明人： Chia-Sheng Lin

IPC分类号： H01L21/70 ,  H01L31/02 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/525 ,  H01L27/146 ,  H01L31/0232 ,  H01L31/18 ,  H01L33/58 ,  H01L33/62 ,  H01L23/00

CPC分类号： H01L31/02005 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14685 ,  H01L31/02327 ,  H01L31/1876 ,  H01L33/58 ,  H01L33/62 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2924/0001 ,  H01L2924/1461 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2924/00

摘要： A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed.

摘要翻译： 公开了一种芯片封装。 所述封装包括具有第一表面和与其相对的第二表面的半导体芯片，与所述第一表面相邻的至少一个导电焊盘以及从所述第二表面向所述第一表面延伸以露出所述导电焊盘的开口。 与第一表面相邻的口径大于与第二表面相邻的开口的口径。 绝缘层和再分配层（RDL）依次设置在第二表面上并延伸到开口的侧壁和底部，RDL通过开口与导电焊盘电连接。 钝化层覆盖RDL并且部分填充开口以在开口中的钝化层和导电垫之间形成空隙。 还公开了芯片封装的制造方法。

公开(公告)号：US09196571B2

公开(公告)日：2015-11-24

申请号：US14592840

申请日：2015-01-08

申请人： XINTEC INC.

发明人： Chia-Sheng Lin ,  Po-Han Lee

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L21/48 ,  H01L23/538 ,  H01L21/784 ,  H01L23/31 ,  H01L23/00 ,  H01L27/146

CPC分类号： H01L23/481 ,  H01L21/481 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/784 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/5389 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014

摘要： A chip device package and a fabrication method thereof are provided. The chip device package includes a semiconductor substrate having a first surface and an opposing second surface. A recessed portion is disposed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the second surface of the semiconductor substrate. A protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion. A through hole is disposed on the first surface of the semiconductor substrate. A buffer material that is different from the material of the protection layer is disposed in the through hole and covered by the protection layer.

摘要翻译： 提供了一种芯片器件封装及其制造方法。 芯片器件封装包括具有第一表面和相对的第二表面的半导体衬底。 凹部与半导体衬底的侧壁相邻地设置，从半导体衬底的第一表面延伸到半导体衬底的至少第二表面。 保护层设置在半导体衬底的第一表面和凹部中。 在半导体衬底的第一表面上设置通孔。 与保护层的材料不同的缓冲材料设置在通孔中并被保护层覆盖。

公开(公告)号：US11705368B2

公开(公告)日：2023-07-18

申请号：US17373773

申请日：2021-07-13

申请人： XINTEC INC.

发明人： Chia-Sheng Lin ,  Hui-Hsien Wu ,  Jian-Hong Chen ,  Tsang-Yu Liu ,  Kuei-Wei Chen

IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L21/02

CPC分类号： H01L21/76894 ,  H01L21/02013 ,  H01L24/94

摘要： A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

公开(公告)号：US09997473B2

公开(公告)日：2018-06-12

申请号：US15409289

申请日：2017-01-18

申请人： XINTEC INC.

发明人： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chaung-Lin Lai

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L21/52 ,  H01L21/54 ,  H01L23/18 ,  H01L23/055 ,  H01L21/48

CPC分类号： H01L23/562 ,  H01L21/4817 ,  H01L21/52 ,  H01L21/54 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/055 ,  H01L23/18 ,  H01L23/3114 ,  H01L23/522 ,  H01L24/16 ,  H01L25/065 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2224/16237

摘要： A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or device region which is adjacent to the first surface. A recess is in the substrate. The recess extends from the second surface towards the first surface, and vertically overlaps the sensing or device region. A redistribution layer is electrically connected to the sensing or device region, and extends from the second surface into the recess. A method of forming the chip package is also provided.