公开(公告)号：US11664800B1

公开(公告)日：2023-05-30

申请号：US16511925

申请日：2019-07-15

Applicant: Xilinx, Inc.

Inventor： VSS Prasad Babu Akurathi ,  Sabarathnam Ekambaram ,  Sasi Rama S. Lanka ,  Hari Bilash Dubey ,  Milind Goel

IPC: H03K17/687

CPC classification number: H03K17/6872

Abstract: A circuit for implementing an input/output connection in an integrated circuit device is described. The circuit comprises a pull-up circuit comprising a first plurality of transistors coupled in series, wherein a gate of a first transistor of the first plurality of transistors is configured to receive a first dynamic bias signal; a pull-down circuit comprising a second plurality of transistors coupled in series, the pull-down circuit being coupled to the pull-up circuit at an output node, wherein a gate of a first transistor of the second plurality of transistors is configured to receive a second dynamic bias signal; and an input/output contact coupled to the output node. A circuit for implementing an input/output connection in an integrated circuit device including a splitter circuit for receiving an input signal on an input pad is also described. A method of implementing an input/output connection in an integrated circuit device is also described.

公开(公告)号：US10003336B1

公开(公告)日：2018-06-19

申请号：US15458678

申请日：2017-03-14

Applicant: Xilinx, Inc.

Inventor： Xiaobao Wang ,  VSS Prasad Babu Akurathi ,  Sasi Rama S. Lanka

IPC: H03K19/017 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/177

CPC classification number: H03K19/0005 ,  H03K19/017509 ,  H03K19/17724 ,  H03K19/17744 ,  H03K19/1776

Abstract: A pull-up leg of disclosed circuitry includes a pull-up pre-driver and a pull-up driver coupled to the pull-up pre-driver. A pull-down leg includes a pull-down pre-driver and a pull-down driver coupled to the pull-down pre-driver. An input/output pad is coupled between the pull-up driver and pull-down driver. A driver-and-termination control circuit is coupled to receive a tristate control signal, a termination control signal, and an input data signal. The driver-and-termination control circuit selects a drive mode, tristate mode, or termination mode in response to the tristate control signal and the termination control signal. The driver-and-termination control circuit drives a first data signal to the pull-up driver and drives a second data signal to the pull-down driver. The first and second data signals have equal logic states in the drive mode and have opposite logic states in the tristate and termination modes.

公开(公告)号：US10484041B2

公开(公告)日：2019-11-19

申请号：US15703800

申请日：2017-09-13

Applicant: Xilinx, Inc.

Inventor： Sabarathnam Ekambaram ,  VSS Prasad Babu Akurathi ,  Milind Goel ,  Hari Bilash Dubey

IPC: H04B1/00 ,  H04B1/58 ,  H04B1/44 ,  H04B1/04 ,  H03K19/0185

Abstract: An example receiver includes: a pad splitter circuit coupled to a pad, the pad splitter circuit configured to generate a first logic signal and a second logic signal; a wide-range receiver coupled to the pad splitter circuit to receive the first and second logic signals, the wide-range receiver comprising a combination of a first Schmitt trigger receiver and a second Schmitt trigger receiver; a control circuit coupled to the pad splitter circuit and the wide-range receiver; and a bias generator circuit coupled to the pad splitter circuit and the wide-range receiver.

公开(公告)号：US20190081656A1

公开(公告)日：2019-03-14

申请号：US15703800

申请日：2017-09-13

Applicant: Xilinx, Inc.

Inventor： Sabarathnam Ekambaram ,  VSS Prasad Babu Akurathi ,  Milind Goel ,  Hari Bilash Dubey

IPC: H04B1/58 ,  H04B1/04 ,  H04B1/00 ,  H04B1/44

CPC classification number: H04B1/586 ,  H03K19/018521 ,  H04B1/005 ,  H04B1/0475 ,  H04B1/44

Abstract: An example receiver includes: a pad splitter circuit coupled to a pad, the pad splitter circuit configured to generate a first logic signal and a second logic signal; a wide-range receiver coupled to the pad splitter circuit to receive the first and second logic signals, the wide-range receiver comprising a combination of a first Schmitt trigger receiver and a second Schmitt trigger receiver; a control circuit coupled to the pad splitter circuit and the wide-range receiver; and a bias generator circuit coupled to the pad splitter circuit and the wide-range receiver.