公开(公告)号：US12190077B2

公开(公告)日：2025-01-07

申请号：US17993464

申请日：2022-11-23

Applicant: XILINX, INC.

Inventor： Sai Ram Venkata Pattabhi Nedunuri ,  Killivalavan Kaliyamoorthy

IPC: G06F5/06 ,  G06F1/10 ,  H04L25/02

Abstract: A communication system includes link circuits that receive serial data over one or more input serial links. The link circuits include a primary link circuit and a secondary link circuit. The secondary link circuit includes a de-serializer circuit configured to receive the serial data from the one or more input serial links and convert the serial data into parallel data, and an aligner circuit comprising a memory. The aligner circuit stops at least one of storing the parallel data in the memory and reading the memory based on a channel bonding signal generated based on a channel bonding symbol within the serial data. The aligner circuit outputs the channel bonding signal to a finite state machine (FSM) circuit of the primary link circuit. The aligner circuit outputs the parallel data based on receiving a read signal from the FSM circuit of the primary link circuit.

公开(公告)号：US20240144897A1

公开(公告)日：2024-05-02

申请号：US17979499

申请日：2022-11-02

Applicant: Xilinx, Inc.

Inventor： Killivalavan Kaliyamoorthy ,  Nedunuri Venkata Pattabhi Sai Ram ,  Phani Krishna Kondepudi ,  Kapil Usgaonkar ,  Pankaj Vasant Kumbhare

IPC: G09G5/399 ,  G09G5/18 ,  H04N5/445

CPC classification number: G09G5/399 ,  G09G5/18 ,  H04N5/44504

Abstract: A clock buffer has a clock-in port that inputs a reference clock and an enable port that inputs a video-clock-enable signal from a video receiver. The clock buffer generates a video pixel clock signal that has pulses of the reference signal as enabled by the video-clock-enable signal. The video receiver includes a link symbol extractor, a link-to-pixel mapper, and a timing generator that work to mirror the actual pixel data rate from the active period in a blanking period and thereby recover the actual video pixel clock.

公开(公告)号：US12183311B2

公开(公告)日：2024-12-31

申请号：US17979499

申请日：2022-11-02

Applicant: Xilinx, Inc.

Inventor： Killivalavan Kaliyamoorthy ,  Nedunuri Venkata Pattabhi Sai Ram ,  Phani Krishna Kondepudi ,  Kapil Usgaonkar ,  Pankaj Vasant Kumbhare

IPC: G09G5/399 ,  G09G5/18 ,  H04N5/445

Abstract: A clock buffer has a clock-in port that inputs a reference clock and an enable port that inputs a video-clock-enable signal from a video receiver. The clock buffer generates a video pixel clock signal that has pulses of the reference signal as enabled by the video-clock-enable signal. The video receiver includes a link symbol extractor, a link-to-pixel mapper, and a timing generator that work to mirror the actual pixel data rate from the active period in a blanking period and thereby recover the actual video pixel clock.