公开(公告)号：US11641323B1

公开(公告)日：2023-05-02

申请号：US17037359

申请日：2020-09-29

Applicant: XILINX, INC.

Inventor： Nguyen Duy Anh Tuan ,  Ji Yang ,  Chengchen Hu ,  Yan Zhang ,  Guanwen Zhong ,  Gordon John Brebner

IPC: H04L47/11 ,  H04L49/901 ,  H04L47/12 ,  H04L41/0803 ,  H04L41/00

Abstract: Examples herein describe an acceleration framework that includes a hybrid congestion control (CC) engine where some components are implemented in software (e.g., a CC algorithm) while other components are implemented in hardware (e.g., measurement and enforcement modules and a flexible processing unit). The hardware components can be designed to provide measurements that can be used by multiple different types of CC algorithms. Depending on which CC algorithms are currently enabled, the hardware components can be programmed to perform measurement, processing, and enforcement tasks, thereby freeing the CPUs in the host to perform other tasks. In this manner, the hybrid CC engine can have the flexibility of a pure software CC algorithm with the advantage of performing many of the operations associated with the CC algorithm in hardware.

公开(公告)号：US11743134B2

公开(公告)日：2023-08-29

申请号：US17065438

申请日：2020-10-07

Applicant: XILINX, INC.

Inventor： Guanwen Zhong ,  Chengchen Hu ,  Gordon John Brebner

IPC: H04L12/24 ,  H04L41/00 ,  H04L43/04 ,  H04L47/22 ,  H04L47/215 ,  H04L47/62

CPC classification number: H04L41/20 ,  H04L43/04 ,  H04L47/22 ,  H04L47/215 ,  H04L47/623

Abstract: Examples herein describe a programmable traffic management engine that includes both programmable and non-programmable hardware components. The non-programmable hardware components are used to generate features that can then be used to perform different traffic management algorithms. Depending on which traffic management algorithm the PTM engine is configured to do, the PTM engine may use a subset (or all) of the features to perform the algorithm. The programmable hardware components in the PTM engine are programmable (e.g., customizable) by the user to perform a selected algorithm using some or all of the features provided by the non-programmable hardware components.

公开(公告)号：US11743051B2

公开(公告)日：2023-08-29

申请号：US17083195

申请日：2020-10-28

Applicant: XILINX, INC.

Inventor： Haris Javaid ,  Ji Yang ,  Sundararajarao Mohan ,  Gordon John Brebner

IPC: H04L9/32 ,  G06F16/23 ,  G06F30/331 ,  H04L9/00

CPC classification number: H04L9/3247 ,  G06F16/2336 ,  G06F30/331 ,  H04L9/321 ,  H04L9/50 ,  H04L2209/125

Abstract: Embodiments herein describe a hardware accelerator for a blockchain node. The hardware accelerator is used to perform a validation operation to validate one or more transactions before those transactions are committed to a ledger of a blockchain. The blockchain may include multiple peer-nodes, each of which contains standard software running on a server or container. Instead of validating a block of transactions using software, the hardware accelerator can validate the transactions in a fraction of the time. The peer-node software then gathers the validation results from the hardware accelerator and combines the results with received block data to derive the block which is committed to the stored ledger.

公开(公告)号：US12050944B2

公开(公告)日：2024-07-30

申请号：US17307747

申请日：2021-05-04

Applicant: XILINX, INC.

Inventor： Guanwen Zhong ,  Chengchen Hu ,  Gordon John Brebner

IPC: G06F9/54 ,  H04L61/2521 ,  H04L69/22

CPC classification number: G06F9/546 ,  H04L61/2525 ,  H04L69/22

Abstract: Embodiments herein describe a describe an interface shell in a SmartNIC that reduces data-copy overhead in CPU-centric solutions that rely on hardware compute engine (which can include one or more accelerators). The interface shell offloads tag matching and address translation without CPU involvement. Moreover, the interface shell enables the compute engine to read messages directly from the network without extra data copy—i.e., without first copying the data into the CPU's memory.

公开(公告)号：US11657040B2

公开(公告)日：2023-05-23

申请号：US17084942

申请日：2020-10-30

Applicant: XILINX, INC.

Inventor： Ji Yang ,  Haris Javaid ,  Sundararajarao Mohan ,  Gordon John Brebner

IPC: G06F16/23 ,  G06F12/0875

CPC classification number: G06F16/2379 ,  G06F12/0875 ,  G06F2212/45

Abstract: Embodiments herein describe a hardware accelerator (e.g., a network acceleration engine) for a blockchain machine or node. The hardware accelerator parses packets containing separate components of a block of transactions to generate data to perform a validation process. To avoid the latency that comes with using software, the embodiments herein describe a protocol processor in the hardware accelerator that parses the packets and prepares the data so it can be consumed by downstream components in the accelerator without software intervention. These downstream components can then perform a validation operation to validate one or more transactions before those transactions are committed (i.e., added) to a ledger of a permissioned blockchain.