知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

98 records (took 0.029 seconds)

    PRE-ENCODING METHOD FOR DNA STORAGE
    1.
    发明公开
    PRE-ENCODING METHOD FOR DNA STORAGE 审中-公开

    公开(公告)号：US20240185021A1

    公开(公告)日：2024-06-06

    申请号：US18355206

    申请日：2023-07-19

    Applicant: Western Digital Technologies, Inc.

    Inventor： Ran Zamir ,  Alexander Bazarsky ,  David Avraham

    IPC: G06N3/00 ,  G16B50/30 ,  G16B50/40

    CPC classification number: G06N3/002 ,  G16B50/30 ,  G16B50/40

    Abstract: A computer-implemented method includes receiving an encoding table defining a plurality of mappings between input segments and encoded segments, where each encoded segment defines an ordered string of data representing a sequence of one or more deoxyribonucleic acid (DNA) nucleotide bases; identifying an input string of input data; segmenting the input string into a plurality of input tuples; for each input tuple, generate a plurality of encoded tuples by identifying an entry of the encoding table that has an input segment equal to the input tuple and adding an encoded tuple that includes an encoded segment; converting the plurality of encoded tuples into a DNA sequence string of DNA nucleotides by concatenating the plurality of encoded tuples in an order defined by the plurality of input tuples; and transmitting the DNA sequence string of DNA nucleotides to be used for synthesizing at least one DNA molecule.

    Key value data placement according to expected reads
    2.
    发明授权
    Key value data placement according to expected reads 有权

    公开(公告)号：US11947830B2

    公开(公告)日：2024-04-02

    申请号：US17747076

    申请日：2022-05-18

    Applicant: Western Digital Technologies, Inc.

    Inventor： David Avraham ,  Alexander Bazarsky ,  Ran Zamir

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data, group a plurality of KV pair data based on a data clustering value, aggregate the grouped plurality of KV pair data, and program the aggregated plurality of KV pair data to the memory device. A length of the KV pair data is less than a size of a flash management unit (FMU). The KV pair data includes a key and a value. Each KV pair data of the plurality of KV pair data has a length less than the size of the FMU. The received KV pair data is stored in a temporary location and grouped together in the temporary location. The grouping is based on a similarity of characteristics of plurality of KV pair data.

    Key value data storage device with improved utilization for short key value pairs
    3.
    发明授权
    Key value data storage device with improved utilization for short key value pairs 有权

    公开(公告)号：US11853564B1

    公开(公告)日：2023-12-26

    申请号：US17843675

    申请日：2022-06-17

    Applicant: Western Digital Technologies, Inc.

    Inventor： David Avraham ,  Alexander Bazarsky ,  Ran Zamir

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/0622 ,  G06F3/0655 ,  G06F3/0679

    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data from a host device, where the KV pair data includes a key and a value, store the received KV pair data in an intermediate storage location, match the received KV pair data to another one or more KV pair data stored in the intermediate storage location, where the matching is based on a utilization parameter of a storage container of the memory device, aggregate the matched received KV pair data and the another one or more KV pair data stored in the intermediate storage location, and program the aggregated KV pair data to the memory device.

    NON-VOLATILE MEMORY DIE WITH DEEP LEARNING NEURAL NETWORK
    9.
    发明申请
    NON-VOLATILE MEMORY DIE WITH DEEP LEARNING NEURAL NETWORK 有权

    公开(公告)号：US20210375358A1

    公开(公告)日：2021-12-02

    申请号：US17405923

    申请日：2021-08-18

    Applicant: Western Digital Technologies, Inc.

    Inventor： Rami Rom ,  Ofir Pele ,  Alexander Bazarsky ,  Tomer Tzvi Eliash ,  Ran Zamir ,  Karin Inbar

    IPC: G11C11/56 ,  G06N3/08 ,  G06N3/063

    Abstract: Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

    Content aware bit flipping decoder
    10.
    发明授权
    Content aware bit flipping decoder 有权

    公开(公告)号：US11057059B1

    公开(公告)日：2021-07-06

    申请号：US16744061

    申请日：2020-01-15

    Applicant: Western Digital Technologies, Inc.

    Inventor： Omer Fainzilber ,  David Avraham ,  Ran Zamir

    IPC: H03M13/45 ,  H03M13/11 ,  G06F11/10

    Abstract: Examples described herein relate generally to content aware bit flipping decoders. An example device includes a decoder. The decoder is configured to: process one or more flip thresholds based on statistics of data to be decoded; and perform a bit flipping algorithm on the data using the one or more processed flip thresholds. Other examples relate to methods of processing one or more flip thresholds based on statistics of data to be decoded and performing a bit flipping algorithm on the data using the one or more processed flip thresholds.

Patent Agency Ranking