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公开(公告)号：US10281758B2
公开(公告)日：2019-05-07
申请号：US15578109
申请日：2017-06-09
Inventor： Chengao Yang
IPC: G06F3/044 , G02F1/1333 , H01L27/20 , H01L41/047 , H01L29/66 , H01L29/786 , H01L41/04 , H01L41/29 , H01L41/113 , H01L27/12 , G02F1/1343 , G02F1/1362 , G02F1/1368 , G06F3/041
Abstract: The present disclosure provides an LTPS array substrate, comprising: a substrate; a gate electrode insulating layer; an interlayer insulating layer; an organic layer; a plurality of pressure sensitive plates formed on the organic layer; a metal layer formed on the organic layer and has a pattern of a plurality of planar touch control signal lines and a plurality of touch pressure control signal lines, wherein the touch pressure control signal lines are connected to the pressure sensitive plates; a passivation layer, wherein a plurality of common electrode plates are formed in the passivation layer, and the planar touch control signal lines are connected to the common electrode plates via a plurality of touch control through-holes.
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Patent Agency Ranking
公开(公告)号：US20180356664A1
公开(公告)日：2018-12-13
申请号：US15578109
申请日：2017-06-09
Inventor： Chengao Yang
IPC: G02F1/1333 , H01L27/12 , H01L29/786 , H01L29/66 , H01L27/20 , H01L41/113 , H01L41/047 , H01L41/04 , H01L41/29 , G06F3/044
CPC classification number: G02F1/13338 , G02F1/134309 , G02F1/136286 , G02F1/1368 , G02F2001/136295 , G02F2001/13685 , G02F2202/104 , G06F3/0412 , G06F3/044 , G06F2203/04103 , G06F2203/04105 , H01L27/1222 , H01L27/124 , H01L27/1248 , H01L27/1259 , H01L27/1262 , H01L27/127 , H01L27/20 , H01L29/66757 , H01L29/78633 , H01L29/78675 , H01L41/042 , H01L41/0475 , H01L41/1132 , H01L41/29
Abstract: The present disclosure provides an LTPS array substrate, comprising: a substrate; a gate electrode insulating layer; an interlayer insulating layer; an organic layer; a plurality of pressure sensitive plates formed on the organic layer; a metal layer formed on the organic layer and has a pattern of a plurality of planar touch control signal lines and a plurality of touch pressure control signal lines, wherein the touch pressure control signal lines are connected to the pressure sensitive plates; a passivation layer, wherein a plurality of common electrode plates are formed in the passivation layer, and the planar touch control signal lines are connected to the common electrode plates via a plurality of touch control through-holes.
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公开(公告)号：US11036099B2
公开(公告)日：2021-06-15
申请号：US16077549
申请日：2018-01-30
Inventor： Chengao Yang
IPC: G02F1/1345 , G06F3/041 , G02F1/1333 , G02F1/1335 , G02F1/1362 , G09G3/36
Abstract: An array substrate includes non-touch-signal-transmitting lines that do not have a function of transmitting a touch signal. The non-touch-signal-transmitting lines are parallel with data lines. By connecting the non-touch-signal-transmitting lines with scan lines, the non-touch-signal-transmitting lines may provide electrical connection between the scan lines and a scan line driving circuit so that the scan line driving circuit and a data line driving chip can be arranged on a same one of edge frame parts or two opposite ones of the edge frame parts. Thus, the other ones of the edge frame parts are allowed to have a width of only 0.1-0.3 mm, making it possible to achieve ultra slimming of edge frame for at least two of the edge frame parts.
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公开(公告)号：US10289231B2
公开(公告)日：2019-05-14
申请号：US15569315
申请日：2017-06-09
Inventor： Chengao Yang
IPC: G06F3/041 , G06F3/047 , H01L27/12 , H01L29/417 , H01L29/423
Abstract: A low temperature poly-silicon (LTPS) array substrate is provided. The LTPS array substrate includes a substrate, a gate electrode insulating layer, an interlayer insulating layer, an organic layer, and a plurality of pressure sensitive plates that are stacked on one another. The pressure sensitive plates are formed on the organic layer. The LTPS array substrate further includes a metal layer formed on the organic layer, and the metal layer has a pattern of a plurality of common electrodes and a plurality of pressure sensitive lines that are insulated from each other. The pressure sensitive lines are connected to the pressure sensitive plates.
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公开(公告)号：US10527895B2
公开(公告)日：2020-01-07
申请号：US15735954
申请日：2017-08-17
Inventor： Chengao Yang
IPC: G02F1/1345 , H01L27/32 , H05K1/02 , H05K1/18
Abstract: The present invention discloses an array substrate, a liquid crystal panel and a liquid crystal display. The array substrate includes a main substrate and an auxiliary substrate, and a plurality of gate scan lines are provided on the main substrate; a gate driver circuit and a plurality of first wires connected to the gate driver circuit are provided on the auxiliary substrate; wherein the auxiliary substrate is bonded to the main substrate so that the plurality of first wires are electrically connected to the plurality of gate scan lines, and the auxiliary substrate is a flexible substrate and is capable of being bent and disposed corresponding to the main substrate. The present invention can realize the ultra-narrow frame of the liquid crystal panel and improve the driving ability of the display.
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公开(公告)号：US10459298B2
公开(公告)日：2019-10-29
申请号：US15735922
申请日：2017-09-21
Inventor： Chengao Yang
IPC: H01L27/12 , G02F1/1345 , G02F1/1333 , G02F1/1362 , G02F1/1343
Abstract: A display device, array substrate and manufacturing method thereof are provided. The array substrate includes an active area and a non-active area, and the active area includes a plurality of scan lines and a plurality of data lines intersecting with the plurality of scan lines, and a plurality of pixel units formed by the intersecting plurality of scan lines and plurality of data lines; the non-active area includes a driving circuit providing scan signals to the scan lines, and the driving circuit is located along an extension direction of the data lines so as to reduce area size of the non-active area along an extension direction of the scan lines to achieve narrowing border size. As such, the ultra-narrow border for display device is achieved.
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