公开(公告)号：US3925804A

公开(公告)日：1975-12-09

申请号：US43765074

申请日：1974-01-29

申请人： WESTINGHOUSE ELECTRIC CORP

发明人： CRICCHI JAMES RONALD ,  RUEHLING BARRY W

IPC分类号： G11C16/04 ,  H01L21/8246 ,  H01L23/29 ,  H01L29/792 ,  H01L29/78 ,  H01L29/34

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L23/29 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00

摘要： The structure of and the method of processing is disclosed for providing a MNOS element comprised of diverse regions within a semiconductive member. A first silicon oxide layer is disposed to cover a first portion of the semiconductive substrate, other than that in which the MNOS element is formed. A second silicon oxide layer is disposed to cover a second portion of the semiconductive member in which the MNOS element is formed. A conductive element is connected to one of the MNOS regions and overlies the first portion of the member. A first layer of a nitride such as Si3N4 is deposited at a rate in the range of 40 to 60 A/minute to cover the silicon oxide layer, whereby a nitride-oxide interface charge of a magnitude and polarity is established to inhibit the formation of a parasitic region within the semiconductive member, due to the application of a voltage signal to the conductive element. In a further aspect, either or both memory and non-memory MNOS elements may be fabricated in a manner to include drain and source regions spaced from each other with its second silicon oxide layer covering the channel formed therebetween, and a gate electrode disposed thereon. In the formation of a memory MNOS element, the second oxide layer covering the second portion of the member is reduced, e.g. by etching, to a thickness in the order of 7 to 9 A. Next, in the fabrication of both memory and non-memory MNOS elements, a second nitride layer is deposited at a rate in the order of 75 to 150 A, whereby the nitride-oxide interface charge is minimized. A plurality of such memory MNOS elements may be formed into a matrix, wherein the row and column conductors are insulated from each other. The deposition of the first nitride layer at the rate specified above inhibits the formation of parasitic regions beneath the row and column conductors. Further, memory and non-memory MNOS elements may be fabricated upon a common semiconductive substrate by simplified fabrication techniques. In particular, the second deposition of silicon nitride is carried out at a rate in the order of 100 A/minute, whereby a minimum nitride-oxide interface charge is established to ensure the effective operation of the non-memory MNOS element and to increase the memory hysteresis window of the memory MNOS element.

摘要翻译： 公开了结构和处理方法，用于提供由半导体构件内的不同区域组成的MNOS元件。 第一氧化硅层设置成覆盖半导体衬底的第一部分，而不是形成MNOS元件的第一氧化硅层。 第二氧化硅层设置成覆盖形成有MNOS元件的半导体部件的第二部分。 导电元件连接到MNOS区域中的一个并且覆盖在构件的第一部分上。 以40〜60A /分钟的速度沉积氮化物如Si 3 N 4的第一层以覆盖氧化硅层，从而建立大小和极性的氮氧化物 - 界面电荷以抑制形成 由于向导电元件施加电压信号，半导体元件内的寄生区域。