公开(公告)号：US20240178285A1

公开(公告)日：2024-05-30

申请号：US18097286

申请日：2023-01-16

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yi-Wei Lien ,  Wei-Chih Cheng ,  Shyh-Chiang Shen ,  Hsin-Chang Tsai

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/408 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/404 ,  H01L29/66462 ,  H01L29/7786

Abstract: A high electron mobility transistor includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate. A source electrode, a gate electrode and a drain electrode are disposed on the semiconductor channel layer. A patterned dielectric layer is disposed on the semiconductor barrier layer, and between the gate electrode and the drain electrode. A first field plate is extended continuously from a side of the patterned dielectric layer to the top surface thereof, and has a step in height. A first dielectric layer is disposed between the semiconductor barrier layer and the patterned dielectric layer. A second dielectric layer covers the patterned dielectric layer. The dielectric constant of the patterned dielectric layer is higher than that of the first dielectric layer and the second dielectric layer.

公开(公告)号：US20250040220A1

公开(公告)日：2025-01-30

申请号：US18226764

申请日：2023-07-26

Applicant: Vanguard International Semiconductor Corporation

Inventor： Chen-Dong Tzou ,  Wei-Chih Cheng ,  Chia-Hao Lee

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: A high electron mobility transistor includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate in sequence. A source electrode and a drain electrode are disposed on the semiconductor channel layer. A semiconductor cap layer is disposed on the semiconductor barrier layer. A first dielectric layer is disposed over the source electrode, the semiconductor cap layer and the drain electrode. A first via passes through the first dielectric layer and is extended downward onto the semiconductor cap layer. A gate electrode is disposed on the first dielectric layer and in contact with the first via. A first field plate is disposed in the first dielectric layer. A second field plate is disposed on the first dielectric layer and in contact with the first field plate.

公开(公告)号：US20240250085A1

公开(公告)日：2024-07-25

申请号：US18098720

申请日：2023-01-19

Applicant: Vanguard International Semiconductor Corporation

Inventor： Wei-Chih Cheng ,  Chia-Hao Lee ,  Chih-Cherng Liao

IPC: H01L27/088 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L27/0883 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42376 ,  H01L29/7786

Abstract: A semiconductor device includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate. A passivation layer covers the semiconductor barrier layer. A first gate electrode and a second gate electrode are laterally separated from each other and at least partially disposed in the passivation layer respectively. Along a first direction, a first gate length of the first gate electrode is less than a second gate length of the second gate electrode. A source electrode and a drain electrode are disposed on the semiconductor channel layer. The second gate electrode is electrically connected to the source electrode. The first gate electrode and the second gate electrode are electrically isolated from each other.