公开(公告)号：US20240243124A1

公开(公告)日：2024-07-18

申请号：US18110353

申请日：2023-02-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Shih-Min Lu ,  Chi-Sheng Tseng ,  Yao-Jhan Wang ,  Chun-Hsien Lin

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823456

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first gate structure on a substrate and then forming a first epitaxial layer adjacent to the first gate structure. Preferably, a top surface of the first epitaxial layer includes a first curve, a second curve, and a third curve connecting the first curve and the second curve, in which the first curve and the second curve include curves concave downward while the third curve includes a curve concave upward.

公开(公告)号：US10373861B1

公开(公告)日：2019-08-06

申请号：US16026077

申请日：2018-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Ying Hsieh ,  Chih-Jung Chen ,  Chien-Hung Chen ,  Chih-Yueh Li ,  Cheng-Pu Chiu ,  Shih-Min Lu ,  Yung-Sung Lin

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.

公开(公告)号：US20190103492A1

公开(公告)日：2019-04-04

申请号：US15722801

申请日：2017-10-02

Applicant: United Microelectronics Corp.

Inventor： Cheng-Pu Chiu ,  Pei-Yu Chen ,  Shih-Min Lu ,  Ming-Yueh Tsai ,  Yung-Sung Lin ,  Te-Chang Hsu ,  Chih-Yi Wang ,  Chi-Hsuan Cheng ,  Sheng-Chen Chung ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66 ,  H01L21/02

Abstract: A method for forming epitaxial material on base material includes forming a stress cap layer on a base layer of a first semiconductor material. Then, a stress is induced on the base layer, wherein the stress is a tensile stress or a compressive stress. The stress cap layer is removed. An epitaxial layer of a second semiconductor material is formed on the base layer, wherein the second semiconductor material is different from the first semiconductor material.