公开(公告)号：US08629794B2

公开(公告)日：2014-01-14

申请号：US13407730

申请日：2012-02-28

申请人： Thomas Saroshan David ,  Bradley Martin ,  Sebastian Ahmed

发明人： Thomas Saroshan David ,  Bradley Martin ,  Sebastian Ahmed

IPC分类号： H03M1/66

CPC分类号： G06F3/005 ,  G06F3/05 ,  H04L7/0008

摘要： An integrated circuit includes a current-based digital-to-analog converter (IDAC) including a clock input and including an output. The integrated circuit further includes a sample synchronization generator to provide a clock signal to a clock output terminal and a first timing signal related to the clock signal to the clock input of the IDAC. The sample synchronization generator controls the clock signal and the first timing signal to communicate a control signal to a peripheral module.

摘要翻译： 集成电路包括基于电流的数模转换器（IDAC），其包括时钟输入并包括输出。 该集成电路还包括一个采样同步发生器，用于向时钟输出端提供时钟信号，以及一个与时钟信号相关的第一定时信号给IDAC的时钟输入。 采样同步发生器控制时钟信号和第一定时信号，以将控制信号传送到外围模块。

公开(公告)号：US20130222165A1

公开(公告)日：2013-08-29

申请号：US13407730

申请日：2012-02-28

申请人： Thomas Saroshan David ,  Bradley Martin ,  Sebastian Ahmed

发明人： Thomas Saroshan David ,  Bradley Martin ,  Sebastian Ahmed

IPC分类号： H03M1/66

CPC分类号： G06F3/005 ,  G06F3/05 ,  H04L7/0008

摘要： An integrated circuit includes a current-based digital-to-analog converter (IDAC) including a clock input and including an output. The integrated circuit further includes a sample synchronization generator to provide a clock signal to a clock output terminal and a first timing signal related to the clock signal to the clock input of the IDAC. The sample synchronization generator controls the clock signal and the first timing signal to communicate a control signal to a peripheral module.

摘要翻译： 集成电路包括基于电流的数模转换器（IDAC），其包括时钟输入并包括输出。 该集成电路还包括一个采样同步发生器，用于向时钟输出端提供时钟信号，以及一个与时钟信号相关的第一定时信号给IDAC的时钟输入。 采样同步发生器控制时钟信号和第一定时信号，以将控制信号传送到外围模块。

公开(公告)号：US20130249724A1

公开(公告)日：2013-09-26

申请号：US13427740

申请日：2012-03-22

申请人： Alan Westwick ,  Sebastian Ahmed

发明人： Alan Westwick ,  Sebastian Ahmed

IPC分类号： H03M1/20

CPC分类号： H03M1/661

摘要： A system and method for generating an analog signal is disclosed. In one embodiment, system includes a first-in, first-out (FIFO) buffer configured to receive and store a plurality of digital values written to the FIFO buffer. The system further includes a digital-to-analog converter (DAC) coupled to read the digital values from the FIFO buffer and configured to convert the digital values to an analog signal. The FIFO buffer is configured to operate in a first mode in which writes to the FIFO buffer are inhibited and current digital values stored in the FIFO buffer are provided to the DAC in a repeating sequence.

摘要翻译： 公开了一种用于产生模拟信号的系统和方法。 在一个实施例中，系统包括被配置为接收和存储写入FIFO缓冲器的多个数字值的先入先出（FIFO）缓冲器。 该系统还包括数模转换器（DAC），其被耦合以读取来自FIFO缓冲器的数字值，并被配置为将数字值转换为模拟信号。 FIFO缓冲器被配置为在第一模式下操作，其中对FIFO缓冲器的写入被禁止，并且存储在FIFO缓冲器中的当前数字值以重复的顺序被提供给DAC。

公开(公告)号：US07911839B2

公开(公告)日：2011-03-22

申请号：US12832774

申请日：2010-07-08

申请人： Sebastian Ahmed

发明人： Sebastian Ahmed

IPC分类号： G11C16/04

CPC分类号： G11C17/18

摘要： Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data.

摘要翻译： 公开了一种控制一次可编程（OTP）存储器的系统和方法。 一种方法可以包括确定集成电路中的硬件能力总线的功能。 该方法还可以包括基于功能将数据存储在集成电路的第一寄存器中。 该方法还可以包括通过基于该数据在集成电路中设置一次可编程存储体中的至少一个位来禁用集成电路中的功能。

公开(公告)号：US07778074B2

公开(公告)日：2010-08-17

申请号：US11726943

申请日：2007-03-23

申请人： Sebastian Ahmed

发明人： Sebastian Ahmed

IPC分类号： G11C16/04

CPC分类号： G11C17/18

摘要： Systems and methods to control one time programmable (OTP) memory are included. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data.

摘要翻译： 包括控制一次可编程（OTP）存储器的系统和方法。 一种方法可以包括确定集成电路中的硬件能力总线的功能。 该方法还可以包括基于功能将数据存储在集成电路的第一寄存器中。 该方法还可以包括通过基于该数据在集成电路中设置一次可编程存储体中的至少一个位来禁用集成电路中的功能。

公开(公告)号：US08723889B2

公开(公告)日：2014-05-13

申请号：US13013660

申请日：2011-01-25

申请人： Xiaohui Wang ,  Sebastian Ahmed

发明人： Xiaohui Wang ,  Sebastian Ahmed

IPC分类号： G09G5/00 ,  G09G5/39

CPC分类号： G09G3/344 ,  G09G5/14 ,  G09G2310/0205 ,  G09G2310/04 ,  G09G2320/0252 ,  G09G2320/10 ,  G09G2340/16

摘要： A display controller including a pixel processor which processes working pixel data for each pixel of a frame, and which includes an overlap detector, a collision detector, and a construction processor. The overlap detector detects an overlap when any new pixel value of a new update region is within a region of a current update of the frame. The collision detector issues a correction request when at least one pixel within the overlap region has a begin pixel value prior to the current update that is different from an end pixel value provided by the current update, and when a new pixel value provided by the new update for the pixel is different from the end pixel value. The construction processor updates the working pixel data before the current update is completed using a new pixel value for each non-overlapping pixel.

摘要翻译： 一种显示控制器，包括处理帧的每个像素的工作像素数据并且包括重叠检测器，碰撞检测器和构造处理器的像素处理器。 当新的更新区域的新像素值在帧的当前更新的区域内时，重叠检测器检测重叠。 当重叠区域内的至少一个像素具有与当前更新提供的结束像素值不同的当前更新之前的开始像素值时，并且当由新的提供的新的像素值时，碰撞检测器发出校正请求 像素的更新与结束像素值不同。 施工处理器在当前更新完成之前使用每个非重叠像素的新像素值更新工作像素数据。

公开(公告)号：US08669892B2

公开(公告)日：2014-03-11

申请号：US13427740

申请日：2012-03-22

申请人： Alan Westwick ,  Sebastian Ahmed

发明人： Alan Westwick ,  Sebastian Ahmed

IPC分类号： H03M1/66

CPC分类号： H03M1/661

摘要： A system and method for generating an analog signal is disclosed. In one embodiment, system includes a first-in, first-out (FIFO) buffer configured to receive and store a plurality of digital values written to the FIFO buffer. The system further includes a digital-to-analog converter (DAC) coupled to read the digital values from the FIFO buffer and configured to convert the digital values to an analog signal. The FIFO buffer is configured to operate in a first mode in which writes to the FIFO buffer are inhibited and current digital values stored in the FIFO buffer are provided to the DAC in a repeating sequence.

摘要翻译： 公开了一种用于产生模拟信号的系统和方法。 在一个实施例中，系统包括被配置为接收和存储写入FIFO缓冲器的多个数字值的先入先出（FIFO）缓冲器。 该系统还包括数模转换器（DAC），其被耦合以读取来自FIFO缓冲器的数字值，并被配置为将数字值转换为模拟信号。 FIFO缓冲器被配置为在第一模式下操作，其中对FIFO缓冲器的写入被禁止，并且存储在FIFO缓冲器中的当前数字值以重复的顺序被提供给DAC。

公开(公告)号：US20120188272A1

公开(公告)日：2012-07-26

申请号：US13013660

申请日：2011-01-25

申请人： Xiaohui Wang ,  Sebastian Ahmed

发明人： Xiaohui Wang ,  Sebastian Ahmed

IPC分类号： G09G5/00

CPC分类号： G09G3/344 ,  G09G5/14 ,  G09G2310/0205 ,  G09G2310/04 ,  G09G2320/0252 ,  G09G2320/10 ,  G09G2340/16

摘要： A display controller including a pixel processor which processes working pixel data for each pixel of a frame, and which includes an overlap detector, a collision detector, and a construction processor. The overlap detector detects an overlap when any new pixel value of a new update region is within a region of a current update of the frame. The collision detector issues a correction request when at least one pixel within the overlap region has a begin pixel value prior to the current update that is different from an end pixel value provided by the current update, and when a new pixel value provided by the new update for the pixel is different from the end pixel value. The construction processor updates the working pixel data before the current update is completed using a new pixel value for each non-overlapping pixel.

摘要翻译： 一种显示控制器，包括处理帧的每个像素的工作像素数据并且包括重叠检测器，碰撞检测器和构造处理器的像素处理器。 当新的更新区域的新像素值在帧的当前更新的区域内时，重叠检测器检测重叠。 当重叠区域内的至少一个像素具有与当前更新提供的结束像素值不同的当前更新之前的开始像素值时，并且当由新的提供的新的像素值时，碰撞检测器发出校正请求 像素的更新与结束像素值不同。 施工处理器在当前更新完成之前使用每个非重叠像素的新像素值更新工作像素数据。

公开(公告)号：US20080232151A1

公开(公告)日：2008-09-25

申请号：US11726943

申请日：2007-03-23

申请人： Sebastian Ahmed

发明人： Sebastian Ahmed

IPC分类号： G11C17/00

CPC分类号： G11C17/18

摘要： Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data.

摘要翻译： 公开了一种控制一次可编程（OTP）存储器的系统和方法。 一种方法可以包括确定集成电路中的硬件能力总线的功能。 该方法还可以包括基于功能将数据存储在集成电路的第一寄存器中。 该方法还可以包括通过基于该数据在集成电路中设置一次可编程存储体中的至少一个位来禁用集成电路中的功能。

公开(公告)号：US08189384B2

公开(公告)日：2012-05-29

申请号：US13026114

申请日：2011-02-11

申请人： Sebastian Ahmed

发明人： Sebastian Ahmed

IPC分类号： G11C16/04

CPC分类号： G11C17/18

摘要： A device includes a one-time-programmable memory including multiple random accessible input/output pins. Each random accessible I/O pin corresponds to a unique memory address in the one-time-programmable memory. The device also includes a multiplexing circuit with multiple inputs. Each of the multiple inputs is coupled to one of the multiple random accessible I/O pins. An output of the multiplexing circuit has a bit width that is less than the number of the multiple random accessible I/O pins.

摘要翻译： 一种设备包括一次性可编程存储器，其包括多个可随机存取的输入/输出引脚。 每个可随机访问的I / O引脚对应于一次性可编程存储器中唯一的存储器地址。 该装置还包括具有多个输入的复用电路。 多个输入中的每一个耦合到多个可随机存取的I / O引脚之一。 复用电路的输出具有小于多个随机可访问I / O引脚的数量的位宽度。