High impedance surface (HIS) enhanced by discrete passives

    公开(公告)号:US11038277B2

    公开(公告)日:2021-06-15

    申请号:US16521477

    申请日:2019-07-24

    Abstract: In one or more embodiments, a high impedance surface (HIS) apparatus comprises a core; a first set of conducting pads, where a first side of the first set of conducting pads is connected to a first side of the core; and a second set of conducting pads, where a first side of the second set of conducting pads is connected to a second side of the core. The apparatus further comprises a plurality of chip inductors, where at least a portion of the chip inductors are connected to a second side of the first set of conducting pads; and a plurality of chip capacitors, where at least a portion of the chip capacitors are connected to a second side of the second set of conducting pads.

    Methods of manufacturing a high impedance surface (HIS) enhanced by discrete passives

    公开(公告)号:US11071213B2

    公开(公告)日:2021-07-20

    申请号:US16521505

    申请日:2019-07-24

    Abstract: In one or more embodiments, a method of manufacturing a high impedance surface (HIS) apparatus comprises patterning a first conducting layer on a core to form a first set of conducting pads, and patterning a second conducting layer on the core to form a second set of conducting pads. The method further comprises applying solder paste to each of the conducting pads of the second set of conducting pads. Also, the method comprises placing chip capacitors on the solder paste on the second set of conducting pads. In addition, the method comprises applying underfill between the chip capacitors. Also, the method comprises applying solder paste to each of the conducting pads of the first set of conducting pads. In addition, the method comprises placing chip inductors on the solder paste on the first set of conducting pads. Further, the method comprises applying underfill between the chip inductors.

    METHODS OF MANUFACTURING A HIGH IMPEDANCE SURFACE (HIS) ENHANCED BY DISCRETE PASSIVES

    公开(公告)号:US20210029836A1

    公开(公告)日:2021-01-28

    申请号:US16521505

    申请日:2019-07-24

    Abstract: In one or more embodiments, a method of manufacturing a high impedance surface (HIS) apparatus comprises patterning a first conducting layer on a core to form a first set of conducting pads, and patterning a second conducting layer on the core to form a second set of conducting pads. The method further comprises applying solder paste to each of the conducting pads of the second set of conducting pads. Also, the method comprises placing chip capacitors on the solder paste on the second set of conducting pads. In addition, the method comprises applying underfill between the chip capacitors. Also, the method comprises applying solder paste to each of the conducting pads of the first set of conducting pads. In addition, the method comprises placing chip inductors on the solder paste on the first set of conducting pads. Further, the method comprises applying underfill between the chip inductors.

    HIGH IMPEDANCE SURFACE (HIS) ENHANCED BY DISCRETE PASSIVES

    公开(公告)号:US20210028550A1

    公开(公告)日:2021-01-28

    申请号:US16521477

    申请日:2019-07-24

    Abstract: In one or more embodiments, a high impedance surface (HIS) apparatus comprises a core; a first set of conducting pads, where a first side of the first set of conducting pads is connected to a first side of the core; and a second set of conducting pads, where a first side of the second set of conducting pads is connected to a second side of the core. The apparatus further comprises a plurality of chip inductors, where at least a portion of the chip inductors are connected to a second side of the first set of conducting pads; and a plurality of chip capacitors, where at least a portion of the chip capacitors are connected to a second side of the second set of conducting pads.

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