公开(公告)号：US20240310868A1

公开(公告)日：2024-09-19

申请号：US18398496

申请日：2023-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory North ,  Sudhakar Surendran ,  Venkatraman Ramakrishnan

IPC: G06F1/06 ,  G06F1/08

CPC classification number: G06F1/06 ,  G06F1/08

Abstract: Embodiments disclosed herein relate to managing clock signals across clock domains. In one implementation, a system is configured to derive a base clock signal from a first clock trigger signal produced by a first subsystem in a first clock domain of the clocking system. The system is further configured to generate a second clock trigger signal based on the base clock signal and a main clock of a second subsystem in a second clock domain of the clocking system. The system is also configured to supply the second clock trigger signal to a second peripheral in the second clock domain.

公开(公告)号：US11775718B2

公开(公告)日：2023-10-03

申请号：US18072842

申请日：2022-12-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhakar Surendran ,  Venkatraman Ramakrishnan

IPC: G06F30/3312 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F119/02 ,  G06F117/04

CPC classification number: G06F30/3312 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F2117/04 ,  G06F2119/02

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

公开(公告)号：US12197840B2

公开(公告)日：2025-01-14

申请号：US17562728

申请日：2021-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhakar Surendran ,  Venkatraman Ramakrishnan

IPC: G06F30/398 ,  G06F30/3312

Abstract: A technique for convergence verification including receiving a data object representation of a first circuit block, receiving one or more assumptions associated with the first circuit block, identifying a synchronization scheme coupled to a port of the first circuit block, determining that the synchronization scheme is within a threshold flip-flop depth, identifying, based on the determination that the synchronization scheme is within the threshold flip-flop depth, a type of the synchronization scheme and a flip-flop depth between the synchronization scheme and the port, generating first convergence information for the first circuit block based on the identified type and flip-flop depth of the synchronization scheme, and outputting the generated convergence information.

公开(公告)号：US20230088503A1

公开(公告)日：2023-03-23

申请号：US18072842

申请日：2022-12-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhakar Surendran ,  Venkatraman Ramakrishnan

IPC: G06F30/3312 ,  G06F30/327

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

公开(公告)号：US20220237355A1

公开(公告)日：2022-07-28

申请号：US17722445

申请日：2022-04-18

Applicant: Texas Instruments Incorporated

Inventor： Sudhakar Surendran

IPC: G06F30/367 ,  G06F30/33 ,  G06F30/3323

Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

公开(公告)号：US12181974B2

公开(公告)日：2024-12-31

申请号：US17563398

申请日：2021-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Veeramanikandan Raju ,  Sudhakar Surendran ,  Anand Kumar G

IPC: G06F11/14 ,  G06F11/07 ,  G06F11/22 ,  G06F11/26 ,  G06F11/30 ,  G06F11/34 ,  G06F11/36 ,  G06F13/16 ,  G06F13/40 ,  G06F21/10 ,  G06F21/60

Abstract: This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.

公开(公告)号：US11531798B2

公开(公告)日：2022-12-20

申请号：US17246136

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Sudhakar Surendran ,  Venkatraman Ramakrishnan

IPC: G06F30/3312 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F119/02 ,  G06F117/04

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

公开(公告)号：US20220269845A1

公开(公告)日：2022-08-25

申请号：US17246136

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Sudhakar Surendran ,  Venkatraman Ramakrishnan

IPC: G06F30/3312 ,  G06F30/327

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

公开(公告)号：US10949594B2

公开(公告)日：2021-03-16

申请号：US16658794

申请日：2019-10-21

Applicant: Texas Instruments Incorporated

Inventor： Sudhakar Surendran

IPC: G06F30/367 ,  G06F30/33 ,  G06F30/3323

Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

公开(公告)号：US20200050724A1

公开(公告)日：2020-02-13

申请号：US16658794

申请日：2019-10-21

Applicant: Texas Instruments Incorporated

Inventor： Sudhakar Surendran

IPC: G06F17/50

Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.