公开(公告)号：US20240256754A1

公开(公告)日：2024-08-01

申请号：US18103859

申请日：2023-01-31

Applicant: Texas Instruments Incorporated

Inventor： Atul Garg ,  Venkatraman Ramakrishnan

IPC: G06F30/398 ,  G06F1/10 ,  G06F30/396

CPC classification number: G06F30/398 ,  G06F1/10 ,  G06F30/396 ,  G06F2111/04

Abstract: A method and computer-implemented system for use with an electronic design automation (EDA) tool to optimize clock scheduling. Based on an initial timing and area optimized design for a logic circuit, an optimal set of clock anchor points on a clock tree for the logic circuit, and slack statistics for a plurality of elements in the logic circuit, are determined. Clock skews for the CAPs associated with the plurality of elements are then scheduled as a function of the slack statistics. A refined timing and area optimized design for the logic circuit is generated based on the clock skews, and the refined timing and area optimized design is utilized as input to a clock tree synthesis module of the EDA tool.