公开(公告)号：US6041400A

公开(公告)日：2000-03-21

申请号：US179147

申请日：1998-10-26

申请人： Taner Ozcelik ,  Shirish Gadre ,  Yew-Koon Tan

发明人： Taner Ozcelik ,  Shirish Gadre ,  Yew-Koon Tan

IPC分类号： G06F15/16 ,  G06F15/173 ,  G06F15/80 ,  G06T1/20 ,  H04N5/14 ,  H04N5/44 ,  G06F19/00

CPC分类号： G06F15/8015

摘要： A circuit arrangement and method utilize a distributed extensible processing architecture to allocate various DSP functions or operations between multiple processing cores disposed on an integrated circuit device. Each processing core includes one or more hardwired datapaths to provide one or more DSP operations. Moreover, each processing core includes a programmable controller that controls the operation of each hardwired datapath via a local computer program executed by the controller. Furthermore, the processing cores are coupled to one another over a communications bus to permit data to be passed between the cores and thereby permit multiple DSP operations to be performed on data supplied to the device.

摘要翻译： 电路布置和方法利用分布式可扩展处理架构来分配在集成电路设备上布置的多个处理核之间的各种DSP功能或操作。 每个处理核心包括一个或多个硬连线数据路径，以提供一个或多个DSP操作。 此外，每个处理核心包括可编程控制器，其通过由控制器执行的本地计算机程序来控制每个硬连线数据路径的操作。 此外，处理核通过通信总线彼此耦合，以允许在核之间传递数据，从而允许对提供给设备的数据执行多个DSP操作。

公开(公告)号：US06263420B1

公开(公告)日：2001-07-17

申请号：US09115187

申请日：1998-07-14

申请人： Yew-Koon Tan ,  Agee Ozeki ,  Tetsuya Fukushima

发明人： Yew-Koon Tan ,  Agee Ozeki ,  Tetsuya Fukushima

IPC分类号： G06F900

CPC分类号： G06F9/30029 ,  G06F9/30032 ,  G06F9/345 ,  G06F9/355

摘要： A digital signal processor particularly adapted for decoding digital audio. The barrel shifter of the processor includes logical circuitry, so that operations involving a combination of a logical operation and a shift, can be performed in a single pass through the combined barrel shifter/logical unit, rather than requiring separate passes through the barrel shifter and ALU, which would require more instruction cycles. The address generator of the processor, includes circuitry which concatenates the most significant bits of a base address of a table to the least significant bits of an index, to thereby rapidly generate addresses of indexed locations in a table.

摘要翻译： 特别适合于解码数字音频的数字信号处理器。 处理器的桶形移位器包括逻辑电路，使得涉及逻辑运算和移位的组合的操作可以在通过组合桶形移位器/逻辑单元的单次传递中执行，而不需要单独通过桶形移位器和 ALU，这将需要更多的指令周期。 处理器的地址生成器包括将表的基地址的最高有效位连接到索引的最低有效位的电路，从而快速地生成表中的索引位置的地址。

公开(公告)号：US06189090B1

公开(公告)日：2001-02-13

申请号：US09094193

申请日：1998-06-09

申请人： Yew-Koon Tan ,  Shuichi Maeda

发明人： Yew-Koon Tan ,  Shuichi Maeda

IPC分类号： G06F940

CPC分类号： G06F9/30181 ,  G06F8/447 ,  G06F9/30076 ,  G06F9/30149 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3816 ,  G06F9/3822

摘要： A digital signal processor which supports an instruction set including both 16-bit instructions and 32-bit instructions, so that particular portions of a program requiring only 16-bit instructions may be encoded in a 16-bit mode, thus reducing the program memory needed to store these portions. The digital signal processor switches between the 16- and 32-bit modes only in response to flow control instructions such as JUMP, CALL or RETURN instructions. JUMP and CALL instructions are coded to indicate the processor mode applicable to the instructions to which the JUMP or CALL instruction goes to, so that the processor may change modes as needed when executing the JUMP or CALL instruction. When a CALL is executed the current processor mode is stored on the processor's stack, so that in response to a RETURN instruction the processor can return to this mode by retrieving the stored mode from the stack.

摘要翻译： 一种数字信号处理器，其支持包括16位指令和32位指令的指令集，使得仅需要16位指令的程序的特定部分可以以16位模式编码，从而减少所需的程序存储器 以存储这些部分。 数字信号处理器仅在响应诸如JUMP，CALL或RETURN指令的流量控制指令时在16位和32位模式之间切换。 JUMP和CALL指令被编码以指示适用于JUMP或CALL指令所指向的指令的处理器模式，使得处理器可以在执行JUMP或CALL指令时根据需要改变模式。 当执行CALL时，当前的处理器模式存储在处理器的堆栈上，因此响应于RETURN指令，处理器可以通过从栈中检索存储的模式返回到该模式。

公开(公告)号：US07012650B2

公开(公告)日：2006-03-14

申请号：US09881404

申请日：2001-06-14

申请人： Fengduo Hu ,  Lin Yin ,  Yew-Koon Tan

发明人： Fengduo Hu ,  Lin Yin ,  Yew-Koon Tan

IPC分类号： H04N9/475

CPC分类号： H04N5/04 ,  H04N5/4401 ,  H04N5/602 ,  H04N21/4302

摘要： The invention uses digital signal processing (DSP) techniques to synchronize an audio encoding process with a video synchronization signal. Namely, the encoder parameters of a DSP microchip are preset according to characteristics of an audio frame. A buffer temporarily stores the audio frame prior to sending it to an encoder. The buffer then transfers the frame in response to receiving a video synchronization signal in conjunction with authorization from a microprocessor. As such, the encoding sequence of the audio frame coincides with the video synchronization signal. Since the corresponding video frame is already slaved to the video synchronization signal, the audio samples are effectively processed in sequence with the video data. Prior to outputting the encoded audio frame to a multiplexor, the encoder sends a value to the microprocessor representing the difference between the end of the encoded audio frame and a second video synchronization signal. Those audio samples are ultimately discarded from the bitstream. Thus, synchronization is achieved by beginning and effectively ending the encoding processes of both the audio and video data, respectively, in sequence with a common video synchronization clock.

公开(公告)号：US5959684A

公开(公告)日：1999-09-28

申请号：US901090

申请日：1997-07-28

申请人： Yew-Koon Tan ,  Gong-san Yu

发明人： Yew-Koon Tan ,  Gong-san Yu

IPC分类号： H04N5/60 ,  G09G5/00 ,  G09G5/12 ,  G11B27/10 ,  H04N5/92 ,  H04N5/93 ,  H04N7/04 ,  H04N7/045 ,  H04N7/26 ,  H04N21/2368 ,  H04N21/434 ,  H04N7/62

CPC分类号： H04N21/4341 ,  H04N19/42 ,  H04N19/44 ,  H04N21/4307

摘要： A method and apparatus for synchronizing the playback of audio and video frames from a program source. The method associates an audio presentation time stamp ("PTS") value with an output audio frame. Selected ones of audio and video data packets include respective audio and video PTS values representing desired playback times of the respective audio and data associated therewith. The selected ones of the audio data packets further include audio frame numbers representing a number of output frames of audio to be played back between the selected ones of the audio data packets. The method comprises the steps of first storing the audio and video PTS values in respective audio and video PTS tables during an audio demultiplexing process. In addition, the audio frame numbers are stored in frame counters in association with respective PTS values during the demultiplexing process. Thereafter, the process sequentially decodes the audio and video input data to produce respective frames of audio and video which are presented to the user. With the presentation of each audio and video frame, the respective audio and video frame counters are selectively decremented. Upon detecting one of the audio frame counters having a zero value, the audio PTS value for that zero value audio frame counter is retrieved. Thereafter, the playback of the audio and video frames is selectively modified so that frames of audio and video are played back in synchronization.

摘要翻译： 一种用于使来自程序源的音频和视频帧的重放同步的方法和装置。 该方法将音频呈现时间戳（“PTS”）值与输出音频帧相关联。 所选择的音频和视频数据分组包括表示与其相关联的相应音频和数据的期望回放时间的相应音频和视频PTS值。 所选择的音频数据分组还包括表示在所选择的音频数据分组之间要播放的音频的输出帧数的音频帧号。 该方法包括以下步骤：在音频解复用处理期间首先将音频和视频PTS值存储在相应的音频和视频PTS表中。 此外，在解复用处理期间，音频帧号与相应的PTS值相关联地存储在帧计数器中。 此后，该处理顺序解码音频和视频输入数据，以产生呈现给用户的相应的音频和视频帧。 随着每个音频和视频帧的呈现，相应的音频和视频帧计数器被选择性地递减。 在检测到具有零值的音频帧计数器之一时，检索该零值音频帧计数器的音频PTS值。 此后，选择性地修改音频和视频帧的重放，使得音频和视频帧同步地重放。