公开(公告)号：US20090091997A1

公开(公告)日：2009-04-09

申请号：US12333913

申请日：2008-12-12

申请人： Takeo Miki ,  Seiji Sawada ,  Masaki TSUKUDE

发明人： Takeo Miki ,  Seiji Sawada ,  Masaki TSUKUDE

IPC分类号： G11C11/401 ,  G11C7/22

CPC分类号： G11C11/406 ,  G11C8/18 ,  G11C11/40615 ,  G11C2211/4061

摘要： A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.

摘要翻译： 触发产生电路提供触发信号。 延迟电路接收触发信号，并提供通过延迟触发信号而产生的延迟信号。 时钟计数器接收时钟，对从接收到触发信号到接收延迟信号的时间段中的接收时钟进行计数，并提供计数结果。 确定电路存储时钟数和等待时间之间的关系，并且确定与从时钟计数器提供的计数结果相对应的等待时间。 延迟寄存器保存所确定的延迟。 WAIT控制电路根据等待时间寄存器中保存的等待时间外部提供WAIT信号。

公开(公告)号：US20110199844A1

公开(公告)日：2011-08-18

申请号：US13081821

申请日：2011-04-07

申请人： Takeo Miki ,  Seiji Sawada ,  Masaki Tsukude

发明人： Takeo Miki ,  Seiji Sawada ,  Masaki Tsukude

IPC分类号： G11C8/18 ,  G11C7/06

CPC分类号： G11C11/406 ,  G11C8/18 ,  G11C11/40615 ,  G11C2211/4061

摘要： A semiconductor memory device for operating in synchronization with a clock is disclosed. The semiconductor includes a memory array having a plurality of memory cells arranged in rows and columns; and a control circuit performing a control, operation to effect row access processing on a selected row and to effect column access processing on column(s). The control being performed in synchronization with a first clock defined by a time of production of the read signal or the write signal according to an externally applied control signal. the control is also performed in synchronization with a second or later clock defined by a latency, to effect the column access processing on a second number of the columns remaining in the burst mode access

摘要翻译： 公开了一种与时钟同步操作的半导体存储器件。 半导体包括具有以行和列排列的多个存储单元的存储器阵列; 以及控制电路，执行控制，对所选择的行进行行访问处理的操作，并对列执行列访问处理。 该控制与根据外部施加的控制信号的读取信号或写入信号的产生时间所限定的第一时钟同步执行。 控制还与由等待时间定义的第二或更迟的时钟同步地执行，以对在突发模式存取中剩余的第二数量的列进行列访问处理

公开(公告)号：US20050169091A1

公开(公告)日：2005-08-04

申请号：US11049059

申请日：2005-02-03

申请人： Takeo Miki ,  Seiji Sawada ,  Masaki Tsukude

发明人： Takeo Miki ,  Seiji Sawada ,  Masaki Tsukude

IPC分类号： G11C11/403 ,  G11C8/00 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C11/407

CPC分类号： G11C11/406 ,  G11C8/18 ,  G11C11/40615 ,  G11C2211/4061

摘要： A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.

摘要翻译： 触发产生电路提供触发信号。 延迟电路接收触发信号，并提供通过延迟触发信号而产生的延迟信号。 时钟计数器接收时钟，对从接收到触发信号到接收延迟信号的时间段中的接收时钟进行计数，并提供计数结果。 确定电路存储时钟数和等待时间之间的关系，并且确定与从时钟计数器提供的计数结果相对应的等待时间。 延迟寄存器保存所确定的延迟。 WAIT控制电路根据等待时间寄存器中保存的等待时间外部提供WAIT信号。

公开(公告)号：US08314970B2

公开(公告)日：2012-11-20

申请号：US12163041

申请日：2008-06-27

申请人： Takeo Miki ,  Takashi Yamaguchi ,  Kenji Miyazaki

发明人： Takeo Miki ,  Takashi Yamaguchi ,  Kenji Miyazaki

IPC分类号： H04N1/405

CPC分类号： H04N1/32309 ,  H04N1/32208 ,  H04N1/32251 ,  H04N1/32256 ,  H04N1/32267 ,  H04N1/32293

摘要： An image processing apparatus according to an embodiment of the invention, includes an image input unit which inputs main image information defined by first, second and third color component information corresponding to at least three colors, a modulation unit which modulates a color difference grid pattern by sub information, a superposing unit which superposes the modulated color difference grid pattern on each of the first, second and third color component information after the modulated color difference grid pattern and each of the first, second and third color component information are rotated relative to each other through a predetermined angle, and a composition unit which composites the first, second and third color component information to generate color image information.

摘要翻译： 根据本发明的实施例的图像处理装置包括：图像输入单元，其输入由至少三种颜色对应的第一，第二和第三颜色分量信息定义的主图像信息;调制单元，其通过 子信息，叠加单元，其在调制色差网格图案之后将调制色差网格图案叠加在第一，第二和第三颜色分量信息中的每一个上，并且第一，第二和第三颜色分量信息中的每一个相对于每个颜色分量信息旋转 另一个通过预定角度，以及合成单元，其合成第一，第二和第三颜色分量信息以生成彩色图像信息。

公开(公告)号：US08175323B2

公开(公告)日：2012-05-08

申请号：US12190798

申请日：2008-08-13

申请人： Takashi Yamaguchi ,  Takeo Miki ,  Kenji Miyazaki

发明人： Takashi Yamaguchi ,  Takeo Miki ,  Kenji Miyazaki

IPC分类号： G06K9/00

CPC分类号： G06T1/0028 ,  G06T2201/0051 ,  G06T2201/0061 ,  G06T2201/0083 ,  H04N1/32272 ,  H04N1/32283 ,  H04N1/32309

摘要： In an image processing apparatus for creating synthetic image information by embedding sub-information in an invisible state in main image information in a visible state, attention pixels in the main image information are set, a specific pixel block is created by assigning a first specific pixel to the attention pixel of a first color and a second specific pixel to the attention pixel of a second color, first key information is selected for a first value of the sub-information constituted by binary information and second key information is selected for a second value, color difference modulation processing is performed on the selected key information based on a predetermined color difference amount, and the color-difference-modulated key information is superposed on the specific pixel block to thereby create the synthetic image information in which the sub-information in an invisible state is embedded in the main image information.

摘要翻译： 在用于通过以可见状态将主要图像信息中的不可见状态嵌入子信息来创建合成图像信息的图像处理装置中，设置主图像信息中的注意像素，通过分配第一特定像素来创建特定像素块 将第一颜色和第二特定像素的关注像素注视到第二颜色的关注像素，对于由二进制信息构成的子信息的第一值选择第一密钥信息，并且为第二值选择第二密钥信息 基于预定的色差量对所选择的密钥信息执行色差调制处理，并且将色差调制密钥信息叠加在特定像素块上，从而创建合成图像信息，其中子信息 在主图像信息中嵌入一个隐形状态。

公开(公告)号：US20120027264A1

公开(公告)日：2012-02-02

申请号：US13151888

申请日：2011-06-02

申请人： Takashi Yamaguchi ,  Takeo Miki ,  Kenji Miyazaki

发明人： Takashi Yamaguchi ,  Takeo Miki ,  Kenji Miyazaki

IPC分类号： G06K9/00

CPC分类号： H04N1/32309 ,  G03G15/507 ,  G03G21/043 ,  H04N1/00005 ,  H04N1/00015 ,  H04N1/00023 ,  H04N1/00031 ,  H04N1/00047 ,  H04N1/0005 ,  H04N1/00063 ,  H04N1/00076 ,  H04N1/29 ,  H04N1/3216

摘要： According to one embodiment, an image processing method for inspecting an image includes creating synthetic image information in which information is synthesized with main image information in a visible state which the human eyes perceive in an invisible state which is hard to perceive with the human eyes, printing the synthetic image information onto a medium, acquiring an image printed on the medium as an inspection image information, extracting information embedded in the main image information from the inspection image acquired, and determining a fault in the image printed on the medium based on an extraction result of information.

摘要翻译： 根据一个实施例，用于检查图像的图像处理方法包括创建合成图像信息，其中以与人眼难以察觉的看不见状态的人眼察觉的可见状态的主图像信息合成信息， 将合成图像信息打印到介质上，获取作为检查图像信息的打印在介质上的图像，从获取的检查图像中提取嵌入在主图像信息中的信息，以及基于打印在介质上的图像中的故障来确定 提取结果信息。

公开(公告)号：US20100139457A1

公开(公告)日：2010-06-10

申请号：US12524170

申请日：2007-11-19

申请人： Takeo Miki ,  Tamotsu Sugimoto ,  Eiichi Sahashi ,  Takamichi Honma ,  Tomoharu Maeseto

发明人： Takeo Miki ,  Tamotsu Sugimoto ,  Eiichi Sahashi ,  Takamichi Honma ,  Tomoharu Maeseto

IPC分类号： C22B58/00

CPC分类号： C22B3/46 ,  C22B7/006 ,  C22B58/00 ,  Y02P10/234

摘要： It is an object to provide a method and an apparatus for recovering indium, the method and apparatus ensuring that it is unnecessary to recover indium in the form of indium hydroxide, indium can be recovered easily by a filter or the like without handling inferiors and also, the recovery rate of indium is greatly improved. The method includes immersing a precipitation-inducing metal which includes zinc and is made into the form of a solid such that any part coming into view three-dimensionally has a longitudinal length of 2.5 to 10 mm in an etching waste solution containing at least indium and ferric chloride and allowed to stand, thereby allowing indium contained in the etching waste solution to precipitate on the surface of the precipitation-inducing metal based on a difference in ionization tendency between zinc and indium, and detaching the indium precipitated on the surface of the precipitation-inducing metal to recover it.

摘要翻译： 本发明的目的是提供一种用于回收铟的方法和装置，该方法和装置确保不需要以铟氢氧化物的形式回收铟，铟可以通过过滤器等容易地回收而不处理下层，还可以 ，铟的回收率大大提高。 该方法包括将包含锌的沉淀诱导金属浸渍并制成固体形式，使得在至少含有铟的蚀刻废液中三维地观察到的纵向长度为2.5至10mm的任何部分，以及 使其静置，由此使蚀刻废液中所含的铟基于锌和铟之间的离子化倾向的差异沉淀在沉淀诱导金属的表面上，并且分离沉淀在沉淀表面上的铟 诱导金属回收。

公开(公告)号：US20070177216A1

公开(公告)日：2007-08-02

申请号：US11700181

申请日：2007-01-31

申请人： Takeo Miki ,  Yoshinori Misumi

发明人： Takeo Miki ,  Yoshinori Misumi

IPC分类号： H04N1/409

CPC分类号： B41J2/325 ,  B41J2/0057

摘要： Two identical images are printed, side by side, on an intermediate transfer-recording medium, by using image data that represents an image to be printed on a brochure. The two images thus printed are compared, thereby to determine whether they have defects. One of the images, which is found to have no defects, is transferred from the intermediate transfer-recording medium to the brochure, which is a final transfer-recording medium.

摘要翻译： 通过使用表示要打印在小册子上的图像的图像数据，将两个相同的图像并排地打印在中间转印记录介质上。 将如此印刷的两张图像进行比较，从而确定它们是否具有缺陷。 发现没有缺陷的图像之一从中间转印记录介质转移到作为最终转印记录介质的小册子。

公开(公告)号：US07102935B2

公开(公告)日：2006-09-05

申请号：US10972537

申请日：2004-10-26

申请人： Takeo Miki ,  Yasuhiko Tsukikawa ,  Shinji Tanaka

发明人： Takeo Miki ,  Yasuhiko Tsukikawa ,  Shinji Tanaka

IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4074 ,  G11C5/14

摘要： Independent power supply systems are provided for a peripheral circuit other than a column decoder, an array-relevant circuit, and a column decoder respectively, so that a peripheral power supply voltage, an array power supply voltage, and a column decoder power supply voltage generated independently of each other are supplied to the peripheral circuit, the array-relevant circuit, and the column decoder as an operating power supply voltage, respectively. Preferably, the column decoder power supply voltage during normal operation is set as an intermediate voltage between the peripheral power supply voltage and the array power supply voltage. Thus, an array configuration suitable for driving a transistor with a low voltage in order to achieve lower power consumption can be obtained.

摘要翻译： 分别为列解码器，阵列相关电路和列解码器之外的外围电路提供独立电源系统，从而产生外围电源电压，阵列电源电压和列解码器电源电压 彼此独立地分别作为工作电源电压提供给外围电路，阵列相关电路和列解码器。 优选地，正常操作期间的列解码器电源电压被设置为外围电源电压和阵列电源电压之间的中间电压。 因此，可以获得适于驱动具有低电压的晶体管以实现更低功耗的阵列配置。

公开(公告)号：US6064607A

公开(公告)日：2000-05-16

申请号：US177484

申请日：1998-10-23

申请人： Takeo Miki ,  Mikio Asakura ,  Satoshi Kawasaki

发明人： Takeo Miki ,  Mikio Asakura ,  Satoshi Kawasaki

IPC分类号： G11C8/10 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C8/10

摘要： Each of first and second program circuits includes a determination node, first to fourth fuses, first to fourth N channel MOS transistors, and first to fourth supply lines. The first to fourth N channel MOS transistors receive first to fourth row address predecode signals, respectively. The first N channel MOS transistor included in the first program circuit and the first N channel MOS transistor included in the second program circuit are arranged adjacent to each other. The first supply line provides a first row address predecode signal to the gate of these two N channel MOS transistors. The same applies for the second to fourth N channel MOS transistors and the second to fourth supply lines. Accordingly, the interconnection capacitance of the row address predecode signal line can be reduced. Also, the size of the transistor driving the row address predecode signal and the transistors in the program circuit can be reduced to allow a smaller layout area for the entire chip.

摘要翻译： 第一和第二编程电路中的每一个包括确定节点，第一至第四保险丝，第一至第四N沟道MOS晶体管和第一至第四电源线。 第一至第四N沟道MOS晶体管分别接收第一至第四行地址预解码信号。 包括在第一编程电路中的第一N沟道MOS晶体管和包括在第二编程电路中的第一N沟道MOS晶体管彼此相邻布置。 第一电源线为这两个N沟道MOS晶体管的栅极提供第一行地址预解码信号。 同样适用于第二至第四N沟道MOS晶体管和第二至第四供电线。 因此，可以减少行地址预解码信号线的互连电容。 此外，可以减小驱动行地址预解码信号的晶体管的尺寸和程序电路中的晶体管的尺寸，以允许整个芯片的布局面积较小。