公开(公告)号：US06307969B1

公开(公告)日：2001-10-23

申请号：US09127610

申请日：1998-07-31

Applicant: Hiroaki Yamashita ,  Kiyoshi Sakai ,  Takahiro Kobayakawa

Inventor： Hiroaki Yamashita ,  Kiyoshi Sakai ,  Takahiro Kobayakawa

IPC: G06K936

CPC classification number: G06T7/238 ,  G06T2207/10016

Abstract: A dynamic image encoding method and an apparatus therefor which apply to a hierarchical motion vector detection process using an SDRAM frame memory. A precedent process is executed sequentially for one rank of a reduced screen obtained after thinning out an input screen to memorize the result, and then a subsequent process is executed sequentially between the input screens for macro blocks of the reduced screen having provided the result of the precedent process so that the precedent and the subsequent process are repeated.

Abstract translation: 一种适用于使用SDRAM帧存储器的分层运动矢量检测处理的动态图像编码方法及其装置。 顺序地执行先前处理，以便在缩小输入屏幕之后获得的缩小屏幕的一等级以存储结果，然后在提供了结果的结果的缩小屏幕的宏块的输入屏幕之间顺序地执行后续处理 以便重复先例和后续过程。

公开(公告)号：US07190674B2

公开(公告)日：2007-03-13

申请号：US10281366

申请日：2002-10-25

Applicant: Takahiro Kobayakawa ,  Hiroaki Yamashita

Inventor： Takahiro Kobayakawa ,  Hiroaki Yamashita

IPC: H04L12/66 ,  H04L12/28 ,  H04L12/26

CPC classification number: H04L49/508 ,  H04L47/22 ,  H04L47/24 ,  H04L47/50 ,  H04L47/56 ,  H04L49/30 ,  H04L49/506

Abstract: In a packet scheduler, an arithmetic-operation controlling means designates output ports in a time-sharing manner and a parallel arithmetic operation means performs an arithmetic operation common with the queues of each designated output port to obtain packet output completion due times (evaluation factors) of the top packets of queues of each output port. Intra-port selecting means selects the evaluation factor of a packet that is to be preferentially output for each output port based on the result of the arithmetic operations. Then inter-port selecting means determines one to be most-preferentially output from the top packets selected based on the selected evaluation factors and the bandwidths for the output ports. Therefore, an apparatus for controlling packet output having such a packet scheduler can realize accurately control bandwidths of a plurality of queues, high-speed processing and the reduced size thereby being incorporated in hardware.

Abstract translation: 在分组调度器中，算术运算控制装置以分时方式指定输出端口，并行算术运算装置执行与各指定输出端口的队列相同的算术运算，以获得分组输出完成到期（评估因子） 的每个输出端口的最高队列数据包。 内部端口选择装置根据算术运算的结果，选择要对每个输出端口优先输出的分组的评估因子。 然后，端口间选择装置根据所选择的评估因子和输出端口的带宽确定从最高分组选出的最优先输出。 因此，具有这种分组调度器的用于控制分组输出的装置可以精确地实现多个队列的控制带宽，高速处理和减小的尺寸，从而被并入硬件。

公开(公告)号：US08643091B2

公开(公告)日：2014-02-04

申请号：US13052028

申请日：2011-03-18

Applicant: Wataru Saito ,  Syotaro Ono ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

Inventor： Wataru Saito ,  Syotaro Ono ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7839 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device includes first, second, third, and fourth semiconductor layers of alternating first and second conductivity types, an embedded electrode in a first trench that penetrates through the second semiconductor layer, a control electrode above the embedded electrode in the first trench, and first and second main electrodes. The fourth semiconductor layer is selectively provided in the first semiconductor layer and is connected to a lower end of a second trench, which penetrates through the second semiconductor layer. The first main electrode is electrically connected to the first semiconductor layer, and the second main electrode is in the second trench and electrically connected to the second, third, and fourth semiconductor layers. The embedded electrode is electrically connected to the second main electrode or the control electrode. A Shottky junction formed of the second main electrode and the first semiconductor layer is formed at a sidewall of the second trench.

Abstract translation: 半导体器件包括交替的第一和第二导电类型的第一，第二，第三和第四半导体层，穿透第二半导体层的第一沟槽中的嵌入电极，在第一沟槽中的嵌入电极上方的控制电极，以及 第一和第二主电极。 第四半导体层选择性地设置在第一半导体层中，并且连接到穿过第二半导体层的第二沟槽的下端。 第一主电极与第一半导体层电连接，第二主电极位于第二沟槽中，并与第二，第三和第四半导体层电连接。 嵌入电极与第二主电极或控制电极电连接。 在第二沟槽的侧壁处形成由第二主电极和第一半导体层形成的肖特基结。

公开(公告)号：US08592917B2

公开(公告)日：2013-11-26

申请号：US13235302

申请日：2011-09-16

Applicant: Syotaro Ono ,  Wataru Saito ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita ,  Toshiyuki Naka

Inventor： Syotaro Ono ,  Wataru Saito ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita ,  Toshiyuki Naka

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238

Abstract: According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.

公开(公告)号：US5918362A

公开(公告)日：1999-07-06

申请号：US883900

申请日：1997-06-27

Applicant: Hiroaki Yamashita ,  Yasuhiro Murasawa

Inventor： Hiroaki Yamashita ,  Yasuhiro Murasawa

IPC: H05K13/04 ,  H05K3/34 ,  H05K13/00 ,  H05K3/30

CPC classification number: H05K13/0069 ,  H05K3/3415 ,  Y10S29/044 ,  Y10T29/53178 ,  Y10T29/53191

Abstract: A jig for dual-side mounting PC boards is composed of a board table which has a board supporting surface, a component receiving hole and a board sucking holes, spacers for placement in the component receiving holes, and a platform having a pressure-reducing space communicating with the board sucking holes. The spacers each have a protrusion for engagement with a spacer positioning hole made in the bottom of the component receiving hole.

Abstract translation: 用于双面安装PC板的夹具由具有板支撑表面的板台，部件接收孔和板吸入孔组成，用于放置在部件接收孔中的间隔件和具有减压空间的平台 与板吸入孔通信。 间隔件各自具有用于与在部件容纳孔的底部形成的间隔物定位孔接合的突起。

公开(公告)号：US4888728A

公开(公告)日：1989-12-19

申请号：US31576

申请日：1987-03-30

Applicant: Masakazu Shirakawa ,  Hiroaki Yamashita ,  Toshio Nishida

Inventor： Masakazu Shirakawa ,  Hiroaki Yamashita ,  Toshio Nishida

IPC: G06F13/00 ,  G06F13/42 ,  G06F15/16 ,  G06F15/177 ,  H04L12/403 ,  H04L29/06 ,  H04L29/08

CPC classification number: H04L12/403 ,  G06F13/423

Abstract: According to a multipoint link data-transmission control system, a master transmission device delivers message data via a bidirectional transmission path to a plurality of slave transmission devices, the data containing a control field for designating control data for setting or resetting a flag. The transmitting of data from the slave transmission device to the master transmission device is allowed when the flag is set, and is inhibited when the flat is reset. Where the transmitting of data from a faulty slave transmission device is to be inhibited, the master transmission device transmits the data to the faculty slave transmission device, by designating flag reset data to the control field of the message data. As a result, a transmission-enable signal, which is delivered in synchronization with a transmission-timing clock signal, is reset, thereby stopping the transmitting of data from the slave transmission device to the master transmission device.

Abstract translation: 根据多点链路数据传输控制系统，主传输设备经由双向传输路径将消息数据传送到多个从属传输设备，该数据包含用于指定用于设置或重置标志的控制数据的控制字段。 当标志被设置时，允许从从属传输设备向主传输设备发送数据，并且当平面被复位时被禁止。 在要禁止从故障从属传输设备发送数据的情况下，主传输设备通过将标志复位数据指定给消息数据的控制字段来将数据发送给教师从属传输设备。 结果，与发送定时时钟信号同步地发送的发送使能信号被复位，从而停止从从属发送装置向主发送装置发送数据。

公开(公告)号：US4794639A

公开(公告)日：1988-12-27

申请号：US834415

申请日：1986-02-28

Applicant: Kiyoshi Urui ,  Hiroaki Yamashita

Inventor： Kiyoshi Urui ,  Hiroaki Yamashita

IPC: H04M11/06 ,  H04M3/42 ,  H04M3/428 ,  H04M3/53 ,  H04M3/533 ,  H04M11/00

CPC classification number: H04M3/5322 ,  H04M3/53316 ,  H04M2201/38 ,  H04M2203/4581 ,  H04M3/428

Abstract: A method and apparatus for automatically transmitting a message to a telephone terminal. Each message is assigned an identification code which identifies a message stored in a calling telephone. When the calling telephone calls the telephone which generated the identification code, the identified message is caused to be displayed to the calling party.

Abstract translation: 一种用于将消息自动发送到电话终端的方法和装置。 每个消息被分配有识别代码，其识别存储在呼叫电话中的消息。 当呼叫电话呼叫产生识别码的电话时，将所识别的消息显示给呼叫方。

公开(公告)号：US09093474B2

公开(公告)日：2015-07-28

申请号：US13600616

申请日：2012-08-31

Applicant: Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

Inventor： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66719 ,  H01L29/7802 ,  H01L29/7811

Abstract: A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

Abstract translation: 电力半导体装置的制造方法包括以下处理。 在第一导电类型的第二半导体层的表面中形成多个第一第二导电型杂质注入层。 在第一非注入区域和多个第一第二导电型杂质注入层中的一个之间形成第一沟槽。 形成第一导电类型的外延层并覆盖多个第一第二导电型杂质注入层。 在外延层的表面形成多个第二第二导电型杂质注入层。 在第二非注入区域和多个第二第二导电型杂质注入层中的一个之间形成第二沟槽。 形成第一导电类型的第三半导体层并且覆盖多个第二第二导电型杂质注入层。

公开(公告)号：US20130248988A1

公开(公告)日：2013-09-26

申请号：US13607697

申请日：2012-09-08

Applicant: Syotaro ONO ,  Wataru Saito ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

Inventor： Syotaro ONO ,  Wataru Saito ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

IPC: H01L29/78 ,  H01L21/02

CPC classification number: H01L29/7827 ,  H01L21/02697 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7802 ,  H01L29/7813

Abstract: A semiconductor device includes a semiconductor substrate and a plurality of gate electrodes including a part extended in a first direction in a plane parallel with the semiconductor substrate. The semiconductor substrate has a second semiconductor layer including a plurality of first conductive type pillars and second conductive type second pillars that are disposed on the first semiconductor layer, extending in the first direction in the plane parallel with the semiconductor substrate and in a third direction intersecting with a second direction orthogonal to the first direction, and arranged adjacent to each other in an alternate manner.

Abstract translation: 半导体器件包括半导体衬底和多个栅电极，其包括在与半导体衬底平行的平面中沿第一方向延伸的部分。 所述半导体衬底具有包括多个第一导电型柱和第二导电型第二柱的第二半导体层，所述第二导电型柱和第二导电型第二柱设置在所述第一半导体层上，在与所述半导体衬底平行的平面中沿所述第一方向延伸，并且在第三方向上相交 具有与第一方向正交的第二方向，并且以交替的方式彼此相邻布置。

公开(公告)号：US20130248979A1

公开(公告)日：2013-09-26

申请号：US13610532

申请日：2012-09-11

Applicant: Syotaro Ono ,  Masaru Izumisawa ,  Hiroshi Ohta ,  Hiroaki Yamashita

Inventor： Syotaro Ono ,  Masaru Izumisawa ,  Hiroshi Ohta ,  Hiroaki Yamashita

IPC: H01L27/088

CPC classification number: H01L29/407 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.

Abstract translation: 根据实施例的功率半导体器件包括其中设置MOSFET元件的元件部分和设置在元件部分周围的端接部分，并且在半导体衬底中分别彼此平行地设置有柱层。 该器件包括第一沟槽和第一绝缘膜。 第一沟槽设置在从MOSFET元件的源电极露出的终端部分的半导体衬底中的柱层的端部之间。 第一绝缘膜设置在第一沟槽的侧表面和底表面上。