公开(公告)号：US11792909B2

公开(公告)日：2023-10-17

申请号：US17322700

申请日：2021-05-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Chih Lai ,  Han-Lung Chang ,  Chi Yang ,  Shang-Chieh Chien ,  Bo-Tsun Liu ,  Li-Jui Chen ,  Po-Chung Cheng

IPC: H05G2/00

CPC classification number: H05G2/006 ,  H05G2/008 ,  H05G2/005

Abstract: A target droplet source for an extreme ultraviolet (EUV) source includes a droplet generator configured to generate target droplets of a given material. The droplet generator includes a nozzle configured to supply the target droplets in a space enclosed by a chamber. The target droplet source further includes a sleeve disposed in the chamber distal to the nozzle. The sleeve is configured to provide a path for the target droplets in the chamber.

公开(公告)号：US20230282614A1

公开(公告)日：2023-09-07

申请号：US17683377

申请日：2022-03-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Der-Chyang Yeh ,  Wei-Chih Lai

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L21/56 ,  H01L24/32 ,  H01L24/73 ,  H01L24/16 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2224/73204 ,  H01L2224/1613 ,  H01L2224/32195

Abstract: A method of forming an integrated circuit package includes following operations. A padding layer is formed on a portion of a carrier. A first semiconductor die is placed on the padding layer and a second semiconductor die is placed on the carrier. The first semiconductor die and the second semiconductor die are encapsulated with a first encapsulation layer. A first redistribution layer structure is formed over the first semiconductor die, the second semiconductor die and the first encapsulation layer. A third semiconductor die is placed on the first redistribution layer structure. The third semiconductor die is encapsulated with a second encapsulation layer. A second redistribution layer structure is formed over the third semiconductor die and the second encapsulation layer. The carrier is debonded. The padding layer is removed, and therefore, a recess is formed in the first encapsulation layer.

公开(公告)号：US20160291482A1

公开(公告)日：2016-10-06

申请号：US14852805

申请日：2015-09-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Tsung Shih ,  Chieh-Jen Cheng ,  Jeng-Horng Chen ,  Chia-Chen Chen ,  Shinn-Sheng Yu ,  Anthony Yen ,  Wei-Chih Lai

IPC: G03F7/20

CPC classification number: G03F7/70641

Abstract: Systems and methods for monitoring the focus of an EUV lithography system are disclosed. Another aspect includes a method having operations of measuring a first shift value for a first patterned set of sub-structures of a focus test structure on a wafer and measuring a second shift value for a second patterned set of sub-structures of the test structure on the wafer. The test structure may be formed on the wafer using asymmetric illumination, with the first patterned set of sub-structures having a first pitch and the second patterned set of sub-structures having a second pitch that is different from the first pitch. The method may further include determining a focus shift compensation for an illumination system based on a difference between the first shift value and the second shift value.

Abstract translation: 公开了用于监测EUV光刻系统的焦点的系统和方法。 另一方面包括一种方法，该方法具有测量晶片上的聚焦测试结构的第一图案化组合子结构的第一移位值并测量第二图案化测试结构的子结构集合的第二移位值 晶圆。 可以使用不对称照明在晶片上形成测试结构，其中第一图案组的子结构具有第一间距，并且第二图案化的子结构组具有不同于第一间距的第二间距。 该方法还可以包括基于第一移位值和第二移位值之间的差异确定照明系统的聚焦偏移补偿。

公开(公告)号：US12193136B2

公开(公告)日：2025-01-07

申请号：US18224005

申请日：2023-07-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Chih Lai ,  Han-Lung Chang ,  Chi Yang ,  Shang-Chieh Chien ,  Bo-Tsun Liu ,  Li-Jui Chen ,  Po-Chung Cheng

IPC: H05G2/00

Abstract: A target droplet source for an extreme ultraviolet (EUV) source includes a droplet generator configured to generate target droplets of a given material. The droplet generator includes a nozzle configured to supply the target droplets in a space enclosed by a chamber. The target droplet source further includes a sleeve disposed in the chamber distal to the nozzle. The sleeve is configured to provide a path for the target droplets in the chamber.

公开(公告)号：US12191224B2

公开(公告)日：2025-01-07

申请号：US17981465

申请日：2022-11-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Chih Lai ,  Chien-Chia Chiu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Tsung-Shu Lin ,  Wei-Cheng Wu ,  Yu-Chen Hsu

IPC: H01L23/367 ,  H01L21/52 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

公开(公告)号：US20230054020A1

公开(公告)日：2023-02-23

申请号：US17981465

申请日：2022-11-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Chih Lai ,  Chien-Chia Chiu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Tsung-Shu Lin ,  Wei-Cheng Wu ,  Yu-Chen Hsu

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L21/52 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/498

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

公开(公告)号：US09823585B2

公开(公告)日：2017-11-21

申请号：US14852805

申请日：2015-09-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Tsung Shih ,  Chieh-Jen Cheng ,  Jeng-Horng Chen ,  Chia-Chen Chen ,  Shinn-Sheng Yu ,  Anthony Yen ,  Wei-Chih Lai

IPC: G03B27/68 ,  G03B27/52 ,  G03F7/20

CPC classification number: G03F7/70641

Abstract: Systems and methods for monitoring the focus of an EUV lithography system are disclosed. Another aspect includes a method having operations of measuring a first shift value for a first patterned set of sub-structures of a focus test structure on a wafer and measuring a second shift value for a second patterned set of sub-structures of the test structure on the wafer. The test structure may be formed on the wafer using asymmetric illumination, with the first patterned set of sub-structures having a first pitch and the second patterned set of sub-structures having a second pitch that is different from the first pitch. The method may further include determining a focus shift compensation for an illumination system based on a difference between the first shift value and the second shift value.