公开(公告)号：US20220271012A1

公开(公告)日：2022-08-25

申请号：US17740308

申请日：2022-05-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Fa Chen ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC分类号： H01L25/065 ,  H01L23/60 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00

摘要： A manufacturing method of a package includes at least the following steps. Contact vias are embedded in a semiconductor carrier. The contact vias are electrically grounded. A first die and a first encapsulant are provided over the semiconductor carrier. The first encapsulant encapsulates the first die. First through insulating vias (TIV) are formed aside the first die. The first TIVs are electrically grounded through the contact vias. The first die, the first encapsulant, and the first TIVs are grinded. A second die is stacked over the first die.

公开(公告)号：US20240088048A1

公开(公告)日：2024-03-14

申请号：US18152153

申请日：2023-01-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Chiang Ting ,  Jian-Wei Hong ,  Sung-Feng Yeh

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L23/5383 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3121 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0655 ,  H01L24/06 ,  H01L24/97 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08237 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80447 ,  H01L2224/97 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/059

摘要： A chip structure provided herein includes a bridge structure including an interconnect bridge, a dielectric layer laterally surrounding the interconnect bridge and through dielectric vias extending from a top of the dielectric layer to a bottom of the dielectric layer, wherein a thickness of the interconnect bridge is identical to a height of each of the through dielectric vias; semiconductor dies disposed on the bridge structure, wherein each of the semiconductor dies overlaps both the interconnect bridge and the dielectric layer and is electrically connected to the interconnect bridge and at least one of the through dielectric vias; and a die support, the semiconductor dies being disposed between the die support and the bridge structure, wherein a sidewall of the die support is coplanar with a sidewall of the bridge structure.

公开(公告)号：US20220139807A1

公开(公告)日：2022-05-05

申请号：US17577035

申请日：2022-01-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Fa Chen ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC分类号： H01L23/48 ,  H01L23/31 ,  H01L23/544 ,  H01L25/00 ,  H01L21/768 ,  H01L21/463 ,  H01L25/065 ,  H01L21/56

摘要： A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.

公开(公告)号：US20240030186A1

公开(公告)日：2024-01-25

申请号：US17872007

申请日：2022-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Der-Chyang Yeh ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L21/56 ,  H01L24/80 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/80895 ,  H01L2224/24011

摘要： A manufacturing method of a package is provided. The method includes the following steps. A wafer substrate having first bonding pads is provided. A die is placed on the wafer substrate, wherein the die comprises second bonding pads bonded to the first bonding pads. The die is encapsulated by an etch stop layer and a first encapsulant. A redistribution structure is disposed over the die, the etch stop layer and the first encapsulant. A portion of the redistribution structure is removed to expose the first encapsulant. The first encapsulant is removed to expose the etch stop layer. A dielectric structure is disposed over the exposed etch stop layer and laterally encapsulates the die and the redistribution structure.

公开(公告)号：US20230298973A1

公开(公告)日：2023-09-21

申请号：US18325104

申请日：2023-05-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Fa Chen ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC分类号： H01L23/48 ,  H01L23/31 ,  H01L23/544 ,  H01L25/00 ,  H01L21/768 ,  H01L21/463 ,  H01L25/065 ,  H01L21/56

CPC分类号： H01L23/481 ,  H01L23/3121 ,  H01L23/544 ,  H01L25/50 ,  H01L21/76804 ,  H01L21/463 ,  H01L25/0657 ,  H01L21/56

摘要： A package includes a semiconductor carrier, a first die, a second die, a redistribution structure, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The redistribution structure is over the second die. The electron transmission path extends from the semiconductor carrier to the redistribution structure. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die, and a third portion of the electron transmission path is aside the second die.

公开(公告)号：US11699638B2

公开(公告)日：2023-07-11

申请号：US17577035

申请日：2022-01-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Fa Chen ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC分类号： H01L21/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/544 ,  H01L25/00 ,  H01L21/768 ,  H01L21/463 ,  H01L25/065 ,  H01L21/56

CPC分类号： H01L23/481 ,  H01L21/463 ,  H01L21/56 ,  H01L21/76804 ,  H01L23/3121 ,  H01L23/544 ,  H01L25/0657 ,  H01L25/50

摘要： A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.