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公开(公告)号:US20240339555A1
公开(公告)日:2024-10-10
申请号:US18745245
申请日:2024-06-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yin-Kai Liao , Jen-Cheng Liu , Kuan-Chieh Huang , Chih-Ming Hung , Yi-Shin Chu , Hsiang-Lin Chen , Sin-Yi Jiang
IPC: H01L31/18 , H01L27/146 , H01L31/0288
CPC classification number: H01L31/1804 , H01L27/14643 , H01L27/14689 , H01L31/0288
Abstract: A method and structure providing an optical sensor having an optimized Ge—Si interface includes providing a substrate having a pixel region and a logic region. In some embodiments, the method further includes forming a trench within the pixel region. In various examples, and after forming the trench, the method further includes forming a doped semiconductor layer along sidewalls and along a bottom surface of the trench. In some embodiments, the method further includes forming a germanium layer within the trench and over the doped semiconductor layer. In some examples, and after forming the germanium layer, the method further includes forming an optical sensor within the germanium layer.
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公开(公告)号:US11508817B2
公开(公告)日:2022-11-22
申请号:US17036287
申请日:2020-09-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yin-Kai Liao , Sin-Yi Jiang , Hsiang-Lin Chen , Yi-Shin Chu , Po-Chun Liu , Kuan-Chieh Huang , Jyh-Ming Hung , Jen-Cheng Liu
IPC: H01L29/10 , H01L29/49 , H01L29/167 , H01L29/66
Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.
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公开(公告)号:US20220102410A1
公开(公告)日:2022-03-31
申请号:US17177696
申请日:2021-02-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Hsiang-Lin Chen , Yi-Shin Chu , Yin-Kai Liao , Sin-Yi Jiang , Kuan-Chieh Huang , Jhy-Jyi Sze
IPC: H01L27/146 , H01L31/105
Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.
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公开(公告)号:US12015099B2
公开(公告)日:2024-06-18
申请号:US17337265
申请日:2021-06-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yin-Kai Liao , Jen-Cheng Liu , Kuan-Chieh Huang , Chih-Ming Hung , Yi-Shin Chu , Hsiang-Lin Chen , Sin-Yi Jiang
IPC: H01L31/18 , H01L27/146 , H01L31/0288
CPC classification number: H01L31/1804 , H01L27/14643 , H01L27/14689 , H01L31/0288
Abstract: A method and structure providing an optical sensor having an optimized Ge—Si interface includes providing a substrate having a pixel region and a logic region. In some embodiments, the method further includes forming a trench within the pixel region. In various examples, and after forming the trench, the method further includes forming a doped semiconductor layer along sidewalls and along a bottom surface of the trench. In some embodiments, the method further includes forming a germanium layer within the trench and over the doped semiconductor layer. In some examples, and after forming the germanium layer, the method further includes forming an optical sensor within the germanium layer.
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公开(公告)号:US11848345B2
公开(公告)日:2023-12-19
申请号:US17177696
申请日:2021-02-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Hsiang-Lin Chen , Yi-Shin Chu , Yin-Kai Liao , Sin-Yi Jiang , Kuan-Chieh Huang , Jhy-Jyi Sze
IPC: H01L27/146 , H01L31/105
CPC classification number: H01L27/14623 , H01L31/1055 , H01L27/14685
Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.
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公开(公告)号:US20210376086A1
公开(公告)日:2021-12-02
申请号:US17036287
申请日:2020-09-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yin-Kai Liao , Sin-Yi Jiang , Hsiang-Lin Chen , Yi-Shin Chu , Po-Chun Liu , Kuan-Chieh Huang , Jyh-Ming Hung , Jen-Cheng Liu
IPC: H01L29/10 , H01L29/66 , H01L29/167 , H01L29/49
Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.
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