公开(公告)号：US11593546B2

公开(公告)日：2023-02-28

申请号：US17404511

申请日：2021-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuang-Hung Chang ,  Yuan-Te Hou ,  Chung-Hsing Wang ,  Yung-Chin Hou

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/20 ,  G06F30/327 ,  H01L23/528 ,  H01L27/088 ,  G06F30/394

Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A total length of the second metal lines of the second net is shorter than a total length of the first metal lines of the first net. A count of the f first metal vias of the first net is less than a count of the second metal vias of the second net.

公开(公告)号：US09799602B2

公开(公告)日：2017-10-24

申请号：US14983797

申请日：2015-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuang-Hung Chang ,  Wen-Hao Chen ,  Yuan-Te Hou ,  Kumar Lalgudi

IPC: H01L23/00 ,  H01L21/76 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5286

Abstract: An integrated circuit includes: a first spine formed on a first conductive layer of the integrated circuit, the spine runs in a first direction; a first plurality of ribs formed on a second conductive layer of the integrated circuit, the first plurality of ribs run parallel to one another in a second direction that is orthogonal to the first direction and overlap respective portions of the first spine; a first plurality of interlayer vias formed between the first and second conductive layers, each of the plurality of interlayer vias electrically couple respective ones of the first plurality of ribs to the first spine at the respective portions of overlap; and a plurality of signal lines formed on the second conductive layer and running parallel to one another in the second direction.

公开(公告)号：US11113443B1

公开(公告)日：2021-09-07

申请号：US16900684

申请日：2020-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuang-Hung Chang ,  Yuan-Te Hou ,  Chung-Hsing Wang ,  Yung-Chin Hou

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/20 ,  G06F30/327 ,  H01L23/528 ,  H01L27/088 ,  G06F30/394

Abstract: An IC structure includes first, second, third and fourth transistors on a substrate, and first and second metallization layers over the transistors. The first metallization layer has a plurality of first metal lines extending laterally along a first direction and having a first line width measured in a second direction. One or more of the first metal lines are part of a first net electrically connecting the first and second transistors. The second metallization layer has a plurality of second metal lines extending laterally along the second direction and having a second line width measured in the first direction and less than the first line width. One or more of the second metal lines are part of a second net electrically connecting the third and fourth transistors, and a total length of the second net is less than a total length of the first net.

公开(公告)号：US12008302B2

公开(公告)日：2024-06-11

申请号：US18173731

申请日：2023-02-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuang-Hung Chang ,  Yuan-Te Hou ,  Chung-Hsing Wang ,  Yung-Chin Hou

IPC: H01L23/528 ,  G06F30/20 ,  G06F30/327 ,  G06F30/337 ,  G06F30/373 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  H01L27/00 ,  H01L27/088

CPC classification number: G06F30/392 ,  G06F30/20 ,  G06F30/327 ,  G06F30/394 ,  H01L23/528 ,  H01L27/0886 ,  G06F30/337 ,  G06F30/373 ,  G06F30/398

Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A count of the first metal vias of the first net is less than a count of the second metal vias of the second net, and a line height of the first metal line of the first net is greater than a line height of the second metal line of the second net.