公开(公告)号：US11410991B2

公开(公告)日：2022-08-09

申请号：US17155268

申请日：2021-01-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/40 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L23/522

摘要： Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

公开(公告)号：US10923467B2

公开(公告)日：2021-02-16

申请号：US16584773

申请日：2019-09-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC分类号： H01L27/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L27/02 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/06 ,  H01L23/522

摘要： Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

公开(公告)号：US20200043912A1

公开(公告)日：2020-02-06

申请号：US16584795

申请日：2019-09-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/40 ,  H01L29/06

摘要： Some embodiments relate to a method. In the method, a semiconductor substrate is provided. Dopant impurities of a first dopant conductivity are implanted into the semiconductor substrate to form a body region. A gate dielectric and a field oxide region are formed over the semiconductor substrate. A polysilicon layer is formed over the gate dielectric and field oxide region. The polysilicon layer is patterned to concurrently form a conductive gate electrode over the gate dielectric and a resistor structure over the field oxide region. The resistor structure is perimeterally bounded by an inner edge of the conductive gate electrode. Dopant impurities of a second dopant conductivity, which is opposite the first dopant conductivity, are implanted into the semiconductor substrate to form a source region and a drain region. The drain region is perimeterally bounded by the inner edge of the conductive gate electrode.

公开(公告)号：US20200027874A1

公开(公告)日：2020-01-23

申请号：US16584773

申请日：2019-09-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/40 ,  H01L29/06

摘要： Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

公开(公告)号：US10483259B2

公开(公告)日：2019-11-19

申请号：US15942728

申请日：2018-04-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC分类号： H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L27/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/40 ,  H01L23/522

摘要： Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

公开(公告)号：US09190476B2

公开(公告)日：2015-11-17

申请号：US14705007

申请日：2015-05-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Ker Hsiao Huo ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng

IPC分类号： H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/404 ,  H01L29/0607 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0852 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7816

摘要： A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

摘要翻译： 横向DMOS晶体管设置有源极区，漏极区和导电栅。 漏极区域通过在导电栅极下方侵入的场氧化物与导电栅极横向分离。 横向DMOS晶体管可以形成为跑道状结构，其中导电栅极包括直线部分和弯曲部分并被源极区域包围。 布置在导电栅极和捕获的漏极之间是一层或多层次的层间电介质材料。 一组或多组隔离的导体引线形成在电介质层中或介质层上，并且可以设置在多个器件级。 隔离导电引线增加了横向DMOS晶体管的击穿电压，特别是在电场拥挤可能会降低击穿电压的弯曲区域中。

公开(公告)号：US09035379B2

公开(公告)日：2015-05-19

申请号：US14333886

申请日：2014-07-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ker Hsiao Huo ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/40 ,  H01L29/417 ,  H01L29/08

CPC分类号： H01L29/404 ,  H01L29/0607 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0852 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7816

摘要： A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

公开(公告)号：US20180226396A1

公开(公告)日：2018-08-09

申请号：US15942728

申请日：2018-04-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L23/522

CPC分类号： H01L27/0288 ,  H01L21/823475 ,  H01L23/5228 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0692 ,  H01L29/405 ,  H01L29/4175 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

公开(公告)号：US09941268B2

公开(公告)日：2018-04-10

申请号：US14208791

申请日：2014-03-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC分类号： H01L29/00 ,  H01L27/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L23/522

CPC分类号： H01L27/0288 ,  H01L21/823475 ,  H01L23/5228 ,  H01L27/0629 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Some embodiments relate to a semiconductor device. The semiconductor device includes a drain region and a channel region surrounding the drain region. A source region surrounds the channel region such that the channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and has an inner edge proximate to the drain. A resistor structure, which is made up of a curved or polygonal path of resistive material, is arranged over the drain and is coupled to the drain. The resistor structure is perimeterally bounded by the inner edge of the gate electrode.

公开(公告)号：US20150262995A1

公开(公告)日：2015-09-17

申请号：US14208791

申请日：2014-03-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC分类号： H01L27/02 ,  H01L23/522 ,  H01L49/02 ,  H01L27/06 ,  H01L21/8234

CPC分类号： H01L27/0288 ,  H01L21/823475 ,  H01L23/5228 ,  H01L27/0629 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Some embodiments relate to a semiconductor device. The semiconductor device includes a drain region and a channel region surrounding the drain region. A source region surrounds the channel region such that the channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and has an inner edge proximate to the drain. A resistor structure, which is made up of a curved or polygonal path of resistive material, is arranged over the drain and is coupled to the drain. The resistor structure is perimeterally bounded by the inner edge of the gate electrode.

摘要翻译： 一些实施例涉及半导体器件。 半导体器件包括漏极区域和围绕漏极区域的沟道区域。 源极区域围绕沟道区域，使得沟道区域将漏极区域与源极区域分离。 栅极电极布置在沟道区域的上方，并且具有靠近漏极的内边缘。 由电阻材料的弯曲或多边形路径构成的电阻器结构布置在漏极上并且耦合到漏极。 电阻器结构由栅电极的内边缘周边界定。