公开(公告)号：US08385627B2

公开(公告)日：2013-02-26

申请号：US11500979

申请日：2006-08-09

申请人： Tadanobu Toba ,  Shuji Kikuchi ,  Yuichi Sakurai ,  Wen Li

发明人： Tadanobu Toba ,  Shuji Kikuchi ,  Yuichi Sakurai ,  Wen Li

IPC分类号： G06K9/00 ,  G06K7/10 ,  G01B5/28 ,  G06F11/30 ,  H04N3/14 ,  G01N21/00

CPC分类号： G06T7/0004 ,  G06T2207/30148

摘要： When an inspection apparatus of a semiconductor device repeatedly executes computation of prescribed area data, such as image processing for detecting defects, procedures for commanding, data load, computation, and data store need to be repeated the number of times of the computation. This may impose a limitation on the speeding up of the operation. In addition, when performing parallel computation by a high-capacity image processing system for handling minute images, a lot of processors are needed, resulting in an increase in cost. In order to solve the above-mentioned problems, in the invention, an inspection apparatus of a semiconductor device includes a data memory including an access section which is capable of reading and writing simultaneously, a plurality of numerical computation units, a connector for connecting the data memory and the numerical computation units, a controller for collectively controlling the contents of processing by the plurality of numerical computation units, another connector for connecting the numerical computation units and the controller, and a data transfer controller for controlling data transfer between the numerical computation units.

摘要翻译： 当半导体装置的检查装置重复执行规定区域数据的计算时，例如用于检测缺陷的图像处理，命令，数据加载，计算和数据存储的过程需要重复计算次数。 这可能对操作的加速施加限制。 此外，当通过大容量图像处理系统执行并行计算以处理微小图像时，需要许多处理器，导致成本增加。 为了解决上述问题，在本发明中，半导体装置的检查装置包括数据存储器，该数据存储器包括能够同时读写的访问部分，多个数值计算单元，连接器 数据存储器和数值计算单元，用于共同控制多个数值计算单元的处理内容的控制器，用于连接数值计算单元和控制器的另一连接器，以及用于控制数值计算之间的数据传送的数据传输控制器 单位。

公开(公告)号：US20070036421A1

公开(公告)日：2007-02-15

申请号：US11500979

申请日：2006-08-09

申请人： Tadanobu Toba ,  Shuji Kikuchi ,  Yuichi Sakurai ,  Wen Li

发明人： Tadanobu Toba ,  Shuji Kikuchi ,  Yuichi Sakurai ,  Wen Li

IPC分类号： G06K9/00

CPC分类号： G06T7/0004 ,  G06T2207/30148

摘要： When an inspection apparatus of a semiconductor device repeatedly executes computation of prescribed area data, such as image processing for detecting defects, procedures for commanding, data load, computation, and data store need to be repeated the number of times of the computation. This may impose a limitation on the speeding up of the operation. In addition, when performing parallel computation by a high-capacity image processing system for handling minute images, a lot of processors are needed, resulting in an increase in cost. In order to solve the above-mentioned problems, in the invention, an inspection apparatus of a semiconductor device includes a data memory including an access section which is capable of reading and writing simultaneously, a plurality of numerical computation units, a connector for connecting the data memory and the numerical computation units, a controller for collectively controlling the contents of processing by the plurality of numerical computation units, another connector for connecting the numerical computation units and the controller, and a data transfer controller for controlling data transfer between the numerical computation units.

摘要翻译： 当半导体装置的检查装置重复执行规定区域数据的计算时，例如用于检测缺陷的图像处理，命令，数据加载，计算和数据存储的过程需要重复计算次数。 这可能对操作的加速施加限制。 此外，当通过大容量图像处理系统执行并行计算以处理微小图像时，需要许多处理器，导致成本增加。 为了解决上述问题，在本发明中，半导体装置的检查装置包括数据存储器，该数据存储器包括能够同时读写的访问部分，多个数值计算单元，连接器 数据存储器和数值计算单元，用于共同控制多个数值计算单元的处理内容的控制器，用于连接数值计算单元和控制器的另一连接器，以及用于控制数值计算之间的数据传送的数据传输控制器 单位。

公开(公告)号：US08032332B2

公开(公告)日：2011-10-04

申请号：US12099868

申请日：2008-04-09

申请人： Yuichi Sakurai ,  Tadanobu Toba ,  Shuji Kikuchi

发明人： Yuichi Sakurai ,  Tadanobu Toba ,  Shuji Kikuchi

IPC分类号： G06F11/00 ,  G01R31/00

CPC分类号： G06F13/4045 ,  G01N21/95684

摘要： A semiconductor inspecting apparatus includes: a buffer memory whose width is matched to the greater of parallel bus width and the width of the number of serial lanes; a preceding stage bus switching unit that fills the buffer memory with input data without making a free space; equivalent transmission capacity conversion including a following stage bus switching unit that fills read data to the width of an arbitrary number of serial lanes without making a free space; a preceding stage bus switching unit that fills a buffer memory with input data without making a free space; and equivalent transmission capacity inverse conversion including a following stage bus switching unit that fills a parallel bus of arbitrary width with data read from a buffer memory without making a free space.

摘要翻译： 半导体检查装置包括：缓冲存储器，其宽度与并行总线宽度越大并且串行数量的宽度相匹配; 前级总线切换单元，其不输入空闲空间来填充缓冲存储器中的输入数据; 等效传输容量转换，包括后级总线切换单元，其将读取的数据填充到任意数量的串行通道的宽度而不产生空闲空间; 前级总线切换单元，其不输入空闲空间来填充具有输入数据的缓冲存储器; 以及等效传输容量逆变换，包括后级总线切换单元，其填充具有从缓冲存储器读取的数据的任意宽度的并行总线，而不产生空闲空间。

公开(公告)号：US20080262760A1

公开(公告)日：2008-10-23

申请号：US12099868

申请日：2008-04-09

申请人： Yuichi Sakurai ,  Tadanobu Toba ,  Shuji Kikuchi

发明人： Yuichi Sakurai ,  Tadanobu Toba ,  Shuji Kikuchi

IPC分类号： G01R31/303

CPC分类号： G06F13/4045 ,  G01N21/95684

摘要： A semiconductor inspecting apparatus includes: a buffer memory whose width is matched to the greater of parallel bus width and the width of the number of serial lanes; a preceding stage bus switching unit that fills the buffer memory with input data without making a free space; equivalent transmission capacity conversion including a following stage bus switching unit that fills read data to the width of an arbitrary number of serial lanes without making a free space; a preceding stage bus switching unit that fills a buffer memory with input data without making a free space; and equivalent transmission capacity inverse conversion including a following stage bus switching unit that fills a parallel bus of arbitrary width with data read from a buffer memory without making a free space.

摘要翻译： 半导体检查装置包括：缓冲存储器，其宽度与并行总线宽度越大并且串行数量的宽度相匹配; 前级总线切换单元，其不输入空闲空间来填充缓冲存储器中的输入数据; 等效传输容量转换，包括后级总线切换单元，其将读取的数据填充到任意数量的串行通道的宽度而不产生空闲空间; 前级总线切换单元，其不输入空闲空间来填充具有输入数据的缓冲存储器; 以及等效传输容量逆变换，包括后级总线切换单元，其填充具有从缓冲存储器读取的数据的任意宽度的并行总线，而不产生空闲空间。

公开(公告)号：US07137055B2

公开(公告)日：2006-11-14

申请号：US11012355

申请日：2004-12-16

申请人： Katsunori Hirano ,  Shuji Kikuchi ,  Yuji Sonoda ,  Wen Li ,  Tadanobu Toba ,  Takashi Kanesaka ,  Masayuki Takahashi

发明人： Katsunori Hirano ,  Shuji Kikuchi ,  Yuji Sonoda ,  Wen Li ,  Tadanobu Toba ,  Takashi Kanesaka ,  Masayuki Takahashi

IPC分类号： G06F11/00

CPC分类号： G11C29/56004 ,  G01R31/31935 ,  G11C29/56

摘要： Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from tho algorithmic pattern generator; a fail address acquisition part for storing an address of the memory under test (fail address) when a result compared by the comparator is failed; a fail address analysis part for analyzing the failed address and calculating the address to be repaired (repair address); and a cycle-pattern generator for redundancy processing for inserting the address to be repaired into a test pattern and applying the address to the memory under test, so that even when capacity of the semiconductor memory is increased, a fabrication yield thereof is raised by testing the memory after the packaging and by performing the redundancy processing of a defective.

摘要翻译： 根据本发明的半导体测试设备包括：算法模式发生器，用于产生用于测试被测存储器的测试模式并将该模式​​应用于被测存储器; 用于比较来自被测存储器的响应信号和来自tho算法模式发生器的期望值的比较器; 当由比较器比较的结果失败时，存储被测存储器的地址（故障地址）的故障地址获取部分; 用于分析故障地址并计算要修复的地址（修复地址）的故障地址分析部分; 以及用于将要修复的地址插入测试图案并将该地址应用于被测存储器的冗余处理的循环模式发生器，使得即使当半导体存储器的容量增加时，其制造成品率通过测试提高 包装后的存储器和通过执行有缺陷的冗余处理。

公开(公告)号：US20050149803A1

公开(公告)日：2005-07-07

申请号：US11012355

申请日：2004-12-16

申请人： Katsunori Hirano ,  Shuji Kikuchi ,  Yuji Sonoda ,  Wen Li ,  Tadanobu Toba ,  Takashi Kanesaka ,  Masayuki Takahashi

发明人： Katsunori Hirano ,  Shuji Kikuchi ,  Yuji Sonoda ,  Wen Li ,  Tadanobu Toba ,  Takashi Kanesaka ,  Masayuki Takahashi

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G01R31/3193 ,  G11C29/44 ,  G11C29/56 ,  G11C29/00 ,  G06F11/00

CPC分类号： G11C29/56004 ,  G01R31/31935 ,  G11C29/56

摘要： Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from tho algorithmic pattern generator; a fail address acquisition part for storing an address of the memory under test (fail address) when a result compared by the comparator is failed; a fail address analysis part for analyzing the failed address and calculating the address to be repaired (repair address); and a cycle-pattern generator for redundancy processing for inserting the address to be repaired into a test pattern and applying the address to the memory under test, so that even when capacity of the semiconductor memory is increased, a fabrication yield thereof is raised by testing the memory after the packaging and by performing the redundancy processing of a defective.

摘要翻译： 根据本发明的半导体测试设备包括：算法模式发生器，用于产生用于测试被测存储器的测试模式并将该模式​​应用于被测存储器; 用于比较来自被测存储器的响应信号和来自tho算法模式发生器的期望值的比较器; 当由比较器比较的结果失败时，存储被测存储器的地址（故障地址）的故障地址获取部分; 用于分析故障地址并计算要修复的地址（修复地址）的故障地址分析部分; 以及用于将要修复的地址插入测试图案并将该地址应用于被测存储器的冗余处理的循环模式发生器，使得即使当半导体存储器的容量增加时，其制造成品率通过测试提高 包装后的存储器和通过执行有缺陷的冗余处理。

公开(公告)号：US07114110B2

公开(公告)日：2006-09-26

申请号：US10413135

申请日：2003-04-15

申请人： Shuji Kikuchi ,  Tadanobu Toba ,  Katsunori Hirano ,  Yuji Sonoda ,  Takeshi Wada

发明人： Shuji Kikuchi ,  Tadanobu Toba ,  Katsunori Hirano ,  Yuji Sonoda ,  Takeshi Wada

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318505 ,  G01R31/31813 ,  G01R31/318511 ,  G01R31/31928 ,  G01R31/31932

摘要： A signature circuit, i.e., a random-number generating circuit, is provided in a memory test apparatus. Also, a signature circuit is provided in each of devices-under-test. This configuration allows the large number of semiconductor integrated-circuit devices to be tested at one time with a high efficiency. This condition realizes a tremendous reduction in the test cost.

公开(公告)号：US20060164115A1

公开(公告)日：2006-07-27

申请号：US10533127

申请日：2003-10-29

申请人： Yasumaro Komiya ,  Shuji Kikuchi ,  Koichi Uesaka ,  Tadanobu Toba ,  Keiichi Yamamoto

发明人： Yasumaro Komiya ,  Shuji Kikuchi ,  Koichi Uesaka ,  Tadanobu Toba ,  Keiichi Yamamoto

IPC分类号： G01R31/26

CPC分类号： G01R31/311

摘要： The present invention aims at performing a semiconductor integrated circuit defect analysis with a simplified analysis apparatus and simplifying a defect analysis work. A defect analysis apparatus for a semiconductor integrated circuit is characterized in that a presence/absence of a defect is detected by irradiating an electromagnetic field from a probe to the semiconductor integrated circuit and detecting an electric characteristic variation such as a power supply current variation in the semiconductor integrated circuit.

摘要翻译： 本发明旨在利用简化的分析装置进行半导体集成电路缺陷分析，并简化缺陷分析工作。 半导体集成电路的缺陷分析装置的特征在于，通过将来自探针的电磁场照射到半导体集成电路来检测缺陷的存在/不存在，并且检测诸如电源电流变化的电特性变化 半导体集成电路。

公开(公告)号：US08168950B2

公开(公告)日：2012-05-01

申请号：US12273805

申请日：2008-11-19

申请人： Kanji Furuhashi ,  Shuji Kikuchi ,  Akira Karakama ,  Yasuhiro Gunji

发明人： Kanji Furuhashi ,  Shuji Kikuchi ,  Akira Karakama ,  Yasuhiro Gunji

IPC分类号： H01J37/28

CPC分类号： H01J37/28 ,  H01J37/20 ,  H01J37/265 ,  H01J2237/20221 ,  H01J2237/20278 ,  H01J2237/2817

摘要： The present invention has a subject to provide an apparatus that optimizes scanning in accordance with circumstances or purposes, reduces distortion of images, and improves throughput, image quality, and defect detection rate by controlling deflection of a charged particle beam in a stage tracking system. To solve this subject, an apparatus according to the present invention is an inspection apparatus for detecting abnormal conditions of an inspection target by irradiating the inspection target with the charged particle beam and detecting generated secondary electrons, including both a stage that moves continuously with the inspection target placed thereon and a deflection control circuit for providing a deflector with a scanning signal that causes the charged particle beam to scan repeatedly in a direction substantially perpendicular to a stage movement axis direction while the charged particle beam being deflected in the stage movement axis direction in accordance with a change in movement speed of the stage during movement of the stage.

摘要翻译： 本发明提供一种根据情况或目的优化扫描的装置，减少图像的失真，并且通过控制在舞台跟踪系统中的带电粒子束的偏转来提高吞吐量，图像质量和缺陷检测率。 为了解决这个问题，根据本发明的装置是一种检查装置，用于通过用带电粒子束照射检查对象并检测产生的二次电子来检测检查对象的异常状况，包括两个检查阶段连续移动的阶段 目标物放置在其上，以及偏转控制电路，用于向偏转器提供扫描信号，该扫描信号使得带电粒子束在基本上垂直于载物台移动轴线方向的方向上反复扫描，同时带电粒子束在载物台移动轴线方向上偏转 根据舞台运动中舞台的移动速度的变化。

公开(公告)号：US4759021A

公开(公告)日：1988-07-19

申请号：US920986

申请日：1986-09-30

申请人： Ikuo Kawaguchi ,  Masaaki Inadachi ,  Shuji Kikuchi

发明人： Ikuo Kawaguchi ,  Masaaki Inadachi ,  Shuji Kikuchi

IPC分类号： G01R31/319 ,  G06F11/22

CPC分类号： G01R31/31921

摘要： In a semiconductor testing device of LSI or the like, a high-speed small-capacity memory (50) is provided in addition to low-speed large-capacity memories (11.about.14) for interleave operation, and test patterns after a branch operation are previously stored in the memory (50). When test patterns are to be read in sequence the reading is performed from the low-speed large-capacity memories (11.about.14), and when branch is produced in the reading sequence the changing is performed to the high-speed small-capacity memory (50) and the test patterns are read from the high-speed small-capacity memory (50) until the reading from the low-speed large-capacity memories (11.about.14) again becomes possible. Thereby, the test patterns of a large number can be outputted without generating a dummy cycle.

摘要翻译： PCT No.PCT / JP86 / 00039 Sec。 371日期1986年9月30日第 102（e）1986年9月30日PCT申请人1986年1月31日PCT公布。 出版物WO86 / 04686 日本1986年8月14日。在LSI等的半导体测试装置中，除了用于交错操作的低速大容量存储器（11差分14）之外还提供高速小容量存储器（50） 并且分支操作之后的测试模式预先存储在存储器（50）中。 当要读取测试图案时，从低速大容量存储器（11差分14）进行读取，并且当在读取顺序中产生分支时，对高速小容量存储器 （50），并且从高速小容量存储器（50）读取测试图案，直到从低速大容量存储器（11差分14）读取再次变为可能。 因此，可以输出大量的测试图案而不产生虚拟周期。