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公开(公告)号：US10892405B2
公开(公告)日：2021-01-12
申请号：US16404978
申请日：2019-05-07
发明人： Ming Li , Yiqi Tang , Jie Chen , Enis Tuncer , Usman Mahmood Chaudhry , Tony Ray Larson , Rajen Manicon Murugan , John Paul Tellkamp , Satyendra Singh Chauhan
摘要： A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.
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公开(公告)号：US20190088628A1
公开(公告)日：2019-03-21
申请号：US16183913
申请日：2018-11-08
IPC分类号： H01L25/07 , H01L23/495 , H01L23/31
摘要： A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.
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公开(公告)号：US11658130B2
公开(公告)日：2023-05-23
申请号：US17138981
申请日：2020-12-31
发明人： Tianyi Luo , Jonathan Almeria Noquil , Satyendra Singh Chauhan , Osvaldo Jorge Lopez , Lance Cole Wright
IPC分类号： H01L23/00 , H01L23/31 , H01L23/495 , H01L21/56 , H01L21/48
CPC分类号： H01L23/562 , H01L21/4825 , H01L21/565 , H01L23/3107 , H01L23/4952 , H01L23/49513 , H01L23/49562 , H01L23/49575
摘要： A packaged electronic device includes a semiconductor die, a conductive plate coupled to a lead, a solder structure and a package structure. The semiconductor die has opposite first and second sides and a terminal exposed along the second side. The conductive plate has opposite first and second sides and an indent that extends into the first side, the conductive plate, and the solder structure extends between the second side of the semiconductor die and the first side of the conductive plate to electrically couple the conductive plate to the terminal, and the solder structure extends into the indent. The package structure encloses the semiconductor die, the conductive plate and a portion of the lead.
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公开(公告)号：US11557722B2
公开(公告)日：2023-01-17
申请号：US17142539
申请日：2021-01-06
发明人： Ming Li , Yiqi Tang , Jie Chen , Enis Tuncer , Usman Mahmood Chaudhry , Tony Ray Larson , Rajen Manicon Murugan , John Paul Tellkamp , Satyendra Singh Chauhan
摘要： A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.
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公开(公告)号：US11495580B2
公开(公告)日：2022-11-08
申请号：US16183913
申请日：2018-11-08
IPC分类号： H01L25/07 , H01L23/495 , H01L23/31
摘要： A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.
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公开(公告)号：US11177197B2
公开(公告)日：2021-11-16
申请号：US16581971
申请日：2019-09-25
摘要： A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.
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公开(公告)号：US20240224415A1
公开(公告)日：2024-07-04
申请号：US18603099
申请日：2024-03-12
发明人： Tianyi Luo , Osvaldo Jorge Lopez , Jonathan Almeria Noquil , Satyendra Singh Chauhan , Bernardo Gallegos
IPC分类号： H05K1/02 , H01L21/50 , H01L21/60 , H01L23/00 , H01L23/538
CPC分类号： H05K1/0271 , H01L21/50 , H01L23/5385 , H01L23/5386 , H01L24/14 , H01L2021/60097 , H01L2224/16225
摘要： In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.
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公开(公告)号：US20210159403A1
公开(公告)日：2021-05-27
申请号：US17142539
申请日：2021-01-06
发明人： Ming Li , Yiqi Tang , Jie Chen , Enis Tuncer , Usman Mahmood Chaudhry , Tony Ray Larson , Rajen Manicon Murugan , John Paul Tellkamp , Satyendra Singh Chauhan
IPC分类号： H01L43/14 , H01L43/06 , G01R15/20 , H01L23/495 , G01R33/07
摘要： A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.
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公开(公告)号：US11930590B2
公开(公告)日：2024-03-12
申请号：US17218792
申请日：2021-03-31
发明人： Tianyi Luo , Osvaldo Jorge Lopez , Jonathan Almeria Noquil , Satyendra Singh Chauhan , Bernardo Gallegos
IPC分类号： H05K1/02 , H01L21/50 , H01L23/00 , H01L23/538 , H01L21/60
CPC分类号： H05K1/0271 , H01L21/50 , H01L23/5385 , H01L23/5386 , H01L24/14 , H01L2021/60097 , H01L2224/16225
摘要： In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.
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公开(公告)号：US20220210911A1
公开(公告)日：2022-06-30
申请号：US17218792
申请日：2021-03-31
发明人： Tianyi Luo , Osvaldo Jorge Lopez , Jonathan Almeria Noquil , Satyendra Singh Chauhan , Bernardo Gallegos
IPC分类号： H05K1/02 , H01L23/00 , H01L23/538 , H01L21/50
摘要： In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.
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