公开(公告)号：US20210176005A1

公开(公告)日：2021-06-10

申请号：US16936065

申请日：2020-07-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sanjay PENNAM ,  Vamsi Krishna KANDALLA ,  Brahmendra Reddy YATHAM ,  Shailesh WARDHEN ,  Jaiganesh BALAKRISHNAN ,  Jawaharlal TANGUDU

IPC: H04L1/00 ,  H04B1/04

Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.

公开(公告)号：US20200162083A1

公开(公告)日：2020-05-21

申请号：US16269473

申请日：2019-02-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sundarrajan RANGACHARI ,  Sriram MURALI ,  Sanjay PENNAM

IPC: H03L7/197 ,  G06F7/58 ,  H03K21/02 ,  H03K21/10 ,  H03K3/84

Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.

公开(公告)号：US20200228126A1

公开(公告)日：2020-07-16

申请号：US16837537

申请日：2020-04-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sundarrajan RANGACHARI ,  Sriram MURALI ,  Sanjay PENNAM

IPC: H03L7/197 ,  G06F7/58 ,  H03K21/02 ,  H03K3/84 ,  H03K21/10

Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.

公开(公告)号：US20210391944A1

公开(公告)日：2021-12-16

申请号：US17462055

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sanjay PENNAM ,  Vamsi Krishna KANDALLA ,  Brahmendra Reddy YATHAM ,  Shailesh WARDHEN ,  Jaiganesh BALAKRISHNAN ,  Jawaharlal TANGUDU

IPC: H04L1/00 ,  H04B1/04

Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.