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    ADJUSTABLE EMBEDDED UNIVERSAL SERIAL BUS 2 LOW-IMPEDANCE DRIVING DURATION
    1.
    发明申请
    ADJUSTABLE EMBEDDED UNIVERSAL SERIAL BUS 2 LOW-IMPEDANCE DRIVING DURATION 有权

    公开(公告)号：US20210311898A1

    公开(公告)日：2021-10-07

    申请号：US17347882

    申请日：2021-06-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Win Naing MAUNG ,  Yonghui TANG ,  Huanzhang HUANG ,  Douglas Edward WENTE

    IPC: G06F13/40 ,  G06F13/42

    Abstract: Aspects of the present disclosure provide for a system. In at least some examples, the system includes an embedded Universal Serial Bus 2 (eUSB2) device having a first receiver and a first transmitter, a processor, a second transmitter coupled to the processor, a second receiver coupled to the processor, a drive low circuit coupled to the processor second transmitter, and differential signal lines having a length greater than ten inches. The differential signal lines are coupled at a first end to the first receiver and the first transmitter and at a second end to the second transmitter and the second receiver. The processor is configured to control the drive low circuit to drive the differential signal lines low with a logic ‘0’ to cause the first receiver to receive the logic ‘0’ and a value of a signal present on the differential signal lines to reach about 0 volts.

    SERIAL BUS SIGNAL CONDITIONER
    3.
    发明申请
    SERIAL BUS SIGNAL CONDITIONER 审中-公开

    公开(公告)号：US20200242071A1

    公开(公告)日：2020-07-30

    申请号：US16751411

    申请日：2020-01-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Win Naing MAUNG ,  Suzanne Mary VINING ,  Yonghui TANG ,  Douglas Edward WENTE ,  Huanzhang HUANG

    IPC: G06F13/42

    Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.

    DIFFERENTIAL DRIVER WITH PULL UP AND PULL DOWN BOOSTERS
    4.
    发明申请
    DIFFERENTIAL DRIVER WITH PULL UP AND PULL DOWN BOOSTERS 有权
    差异驱动器，拉起和拉下推杆

    公开(公告)号：US20160087633A1

    公开(公告)日：2016-03-24

    申请号：US14847264

    申请日：2015-09-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Weicheng ZHANG ,  Huanzhang HUANG ,  Yanli FAN ,  Roland SPERLICH

    IPC: H03K19/0944

    CPC classification number: H03K19/0944 ,  H03K19/018578

    Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.

    Abstract translation: 驱动器包括耦合到电源电压的第一和第二电阻器，并且耦合到正和负输出节点处的主晶体管对。 第一和第二对主晶体管对正和负输出节点提供强调和去加重。 该驱动器还包括一个延迟逆变器，一个上拉升压器和一个下拉式升压器。 延迟反相器延迟并反相一对差分输入信号，以提供延迟和反相的差分信号。 上拉升压器提供绕过第一和第二电阻器但包括第一和第二对主晶体管中的至少一些的旁路电流路径。 下拉升压器提供从电源电压通过第一或第二电阻到地的附加电流路径。

    LOSS OF SIGNAL DETECTION CIRCUIT
    5.
    发明申请
    LOSS OF SIGNAL DETECTION CIRCUIT 审中-公开

    公开(公告)号：US20200350899A1

    公开(公告)日：2020-11-05

    申请号：US16936462

    申请日：2020-07-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Huanzhang HUANG ,  Amit RANE

    IPC: H03K17/00 ,  G06F13/38 ,  H03K19/003 ,  H03K17/56

    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

    DELAY CELL
    6.
    发明申请
    DELAY CELL 审中-公开

    公开(公告)号：US20200059224A1

    公开(公告)日：2020-02-20

    申请号：US16367381

    申请日：2019-03-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Yanfei JIANG ,  Huanzhang HUANG ,  Yonghui TANG ,  Shita GUO

    IPC: H03K5/00 ,  H03K5/1252 ,  G05F1/46 ,  H03K19/20 ,  H03K19/0175

    Abstract: Aspects of the disclosure provide for a method. In some examples, the method includes detecting a transition in an input signal (IN), generating a bias current based on the detected transition in IN, and modifying a charge status of a capacitor based on the charge current. The method further includes generating an output signal (OUT) based on the charge status of the capacitor, disabling the bias current generation based on values of IN and OUT, and strongly pulling the capacitor up or down based on the disabling the bias current generation.

    LOSS OF SIGNAL DETECTION CIRCUIT
    7.
    发明申请
    LOSS OF SIGNAL DETECTION CIRCUIT 审中-公开

    公开(公告)号：US20200052684A1

    公开(公告)日：2020-02-13

    申请号：US16535557

    申请日：2019-08-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Huanzhang HUANG ,  Amit RANE

    IPC: H03K17/00 ,  G06F13/38 ,  H03K17/56 ,  H03K19/003

    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

    LOSS OF SIGNAL DETECTION CIRCUIT
    8.
    发明申请
    LOSS OF SIGNAL DETECTION CIRCUIT 有权

    公开(公告)号：US20210159896A1

    公开(公告)日：2021-05-27

    申请号：US17163894

    申请日：2021-02-01

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Huanzhang HUANG ,  Amit RANE

    IPC: H03K17/00 ,  G06F13/38 ,  H03K19/003 ,  H03K17/56

    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

    EMBEDDED UNIVERSAL SERIAL BUS 2 REPEATER
    9.
    发明申请
    EMBEDDED UNIVERSAL SERIAL BUS 2 REPEATER 审中-公开

    公开(公告)号：US20200073839A1

    公开(公告)日：2020-03-05

    申请号：US16404494

    申请日：2019-05-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Win Naing MAUNG ,  Douglas Edward WENTE ,  Mustafa Ulvi ERDOGAN ,  Huanzhang HUANG ,  Saurabh GOYAL ,  Bhupendra SHARMA

    IPC: G06F13/38 ,  G06F13/42 ,  H04B3/36

    Abstract: Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.

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