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1.发明公开公开(公告)号：US20240030900A1
公开(公告)日：2024-01-25
申请号：US17872841
申请日：2022-07-25
发明人： Srijan Rastogi , Sumantra Seth , Baher Haroun
CPC分类号： H03K3/01 , H03F3/45475
摘要： A driver system includes a non-inverting system input, an inverting system input, a non-inverting system output and an inverting system output. The driver system includes a line driver which includes a non-inverting driver input coupled to the non-inverting system input and includes an inverting driver input coupled to the inverting system input. The line driver includes an inverting driver output and a non-inverting driver output. The driver system includes a first termination resistor coupled between the non-inverting driver output and the non-inverting system output and includes a second termination resistor coupled between the inverting driver output and the inverting system output. The driver system includes a first amplifier stage coupled to the line driver and includes a second amplifier stage coupled to the line driver.
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公开(公告)号：US11716056B2
公开(公告)日：2023-08-01
申请号：US17109763
申请日：2020-12-02
发明人： Tolga Dinc , Sachin Kalia , Swaminathan Sankaran , Baher Haroun
CPC分类号： H03F1/02 , H03F3/45475 , H03F2200/09 , H03F2200/541
摘要： A system includes a first differential amplifier and a first transformer with a primary coil coupled to an output of the first differential amplifier and with a secondary coil coupled to a load. The system also includes a second differential amplifier and a second transformer with a primary coil coupled to an output of the second differential amplifier and with a secondary coil coupled in series with the secondary coil of the first transformer. The system also includes a tuning network coupled to a center tap node between the secondary coil of the first transformer and the secondary coil of the second transformer.
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公开(公告)号：US11460551B2
公开(公告)日：2022-10-04
申请号：US16287411
申请日：2019-02-27
发明人： Baher Haroun , Rahmi Hezar , Srinath Ramaswamy , Nirmal C. Warke , David Magee , Ting Li
IPC分类号： G01S7/481 , G01S17/10 , G01S7/4865 , G01S7/484
摘要： A pulsed light source illuminates a scene with a virtual array of points. Light reflected by the scene is detected by a small pixel array, allowing generation of a three-dimensional map of the scene. A processing element processing data output by the small pixel array uses a multipath resolution algorithm to resolve individual objects in the scene.
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公开(公告)号：US11342928B1
公开(公告)日：2022-05-24
申请号：US17460575
申请日：2021-08-30
摘要： A method, providing an oscillator output signal to reference inputs of a PLL and an output clock circuit; providing a first divisor value to a control input of the PLL to regulate a closed loop that includes a physics cell, a receiver, and the PLL; providing a second divisor value to a control input of the output clock circuit to control an output frequency of an output clock signal; shifting the first divisor value in a first direction to cause a perturbation in the closed loop; shifting the second divisor value in an opposite second direction to counteract a response of the closed loop to the perturbation and to regulate the output frequency of the output clock signal; and based on the receiver output signal, analyzing the response of the closed loop to the perturbation.
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公开(公告)号：US20210065830A1
公开(公告)日：2021-03-04
申请号：US17003185
申请日：2020-08-26
发明人： Ashwin Raghunathan , Marco Corsi , Baher Haroun , Seyed Miaad Seyed Aliroteh , Swaminathan Sankaran , Robert Floyd Payne
摘要： A track and hold circuit includes a signal input terminal, a clock input terminal, an output terminal, a transistor, and a bootstrapping circuit with a transformer. The transistor includes a source, a drain, and a gate, where the source is coupled to the signal input terminal, and the drain is coupled to the output terminal. The transformer includes a primary winding coupled to the clock input terminal, and a secondary winding. The secondary winding is coupled between the source and the gate to control a gate-source voltage of the transistor.
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公开(公告)号：US20210044300A1
公开(公告)日：2021-02-11
申请号：US17080879
申请日：2020-10-27
发明人： Baher Haroun , Wenting Zhou , Kai Yiu Tam , Reza Hoshyar , Ali Kiaei
摘要： A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.
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公开(公告)号：US20200212899A1
公开(公告)日：2020-07-02
申请号：US16585155
申请日：2019-09-27
发明人： Tolga Dinc , Salvatore Luciano Finocchiaro , Gerd Schuppener , Siraj Akhtar , Swaminathan Sankaran , Baher Haroun
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to provide phase imbalance correction. An example system includes a phase detector to obtain a first signal and generate a first output, a comparator coupled to the phase detector, the comparator to generate a second output based on the first output, and an amplifier coupled to the comparator, the amplifier to adjust a first phase response of the first signal based on the second output.
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公开(公告)号：US10547438B2
公开(公告)日：2020-01-28
申请号：US15858537
申请日：2017-12-29
摘要： A circuit includes a serializer module that includes an input stage that samples an input signal to capture an edge location for each of the input signal in a given time frame. An edge encoder encodes the edge location for the input signal into a packet frame to specify where the edge location occurs in the given time frame for the input signal. A transmitter receives the packet frame from the edge decoder and converts the packet frame into a serial data stream. The transmitter communicates the edge location for the input signal via the serial data stream.
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公开(公告)号：US10547268B2
公开(公告)日：2020-01-28
申请号：US15858485
申请日：2017-12-29
发明人： Tobias Bernhard Fritz , Martin Staebler , Baher Haroun , Peter Fundaro , Jiri Panacek , Ralf Peter Brederlow
摘要： A motor drive circuit includes a first serializer-deserializer (SER-DES) module that converts first SER-DES input signals into a first SER-DES output serial data stream. The first SER-DES input signals relate to motor control inputs or motor drive power outputs. A second SER-DES module converts a second SER-DES input serial data stream corresponding to the first SER-DES output serial data stream into second SER-DES output signals. The second SER-DES input signals relate to motor drive power outputs or motor control inputs. A serial isolation channel provides a galvanic isolation barrier between the first SER-DES module and the second SER-DES module. The serial isolation channel communicates the first SER-DES output serial data stream across the galvanic isolation barrier to provide the second SER-DES input serial data stream.
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公开(公告)号：US10461810B2
公开(公告)日：2019-10-29
申请号：US15638212
申请日：2017-06-29
发明人： Benjamin Stassen Cook , Nathan Brooks , Swaminathan Sankaran , Bradley Allen Kramer , Mark W. Morgan , Baher Haroun
摘要： A system is provided in which a set of modules each have a substrate on which is mounted a radio frequency (RF) transmitter and/or an RF receiver coupled to a near field communication (NFC) coupler located on the substrate. Each module has a housing that surrounds and encloses the substrate. The housing has a port region on a surface of the housing. Each module has a field confiner located between the NFC coupler and the port region on the housing configured to guide electromagnetic energy emanated from the NFC coupler through the port region to a port region of an adjacent module. A reflective surface is positioned adjacent the backside of each NFC coupler to reflect back side electromagnetic towards the port region.
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