公开(公告)号：US20210065830A1

公开(公告)日：2021-03-04

申请号：US17003185

申请日：2020-08-26

申请人： Texas Instruments Incorporated

发明人： Ashwin Raghunathan ,  Marco Corsi ,  Baher Haroun ,  Seyed Miaad Seyed Aliroteh ,  Swaminathan Sankaran ,  Robert Floyd Payne

IPC分类号： G11C27/02 ,  H03M1/06 ,  H03M1/12

摘要： A track and hold circuit includes a signal input terminal, a clock input terminal, an output terminal, a transistor, and a bootstrapping circuit with a transformer. The transistor includes a source, a drain, and a gate, where the source is coupled to the signal input terminal, and the drain is coupled to the output terminal. The transformer includes a primary winding coupled to the clock input terminal, and a secondary winding. The secondary winding is coupled between the source and the gate to control a gate-source voltage of the transistor.

公开(公告)号：US11322217B2

公开(公告)日：2022-05-03

申请号：US17003185

申请日：2020-08-26

申请人： Texas Instruments Incorporated

发明人： Ashwin Raghunathan ,  Marco Corsi ,  Baher Haroun ,  Seyed Miaad Seyed Aliroteh ,  Swaminathan Sankaran ,  Robert Floyd Payne

IPC分类号： G11C27/00 ,  G11C27/02 ,  H03K17/06 ,  H03M1/12 ,  H03M1/06

摘要： A track and hold circuit includes a signal input terminal, a clock input terminal, an output terminal, a transistor, and a bootstrapping circuit with a transformer. The transistor includes a source, a drain, and a gate, where the source is coupled to the signal input terminal, and the drain is coupled to the output terminal. The transformer includes a primary winding coupled to the clock input terminal, and a secondary winding. The secondary winding is coupled between the source and the gate to control a gate-source voltage of the transistor.