公开(公告)号：US11012057B2

公开(公告)日：2021-05-18

申请号：US16294726

申请日：2019-03-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kai-Chi Huang ,  Jerry Chang Jui Kao ,  Chi-Lin Liu ,  Lee-Chung Lu ,  Shang-Chih Hsieh ,  Wei-Hsiang Ma ,  Yung-Chen Chien

IPC: H03K3/037 ,  G06F1/3237 ,  H03K19/00 ,  H03K3/356

Abstract: A circuit includes a slave latch including a first input and an output, the first input being coupled to a master latch, and a retention latch including a second input coupled to the output. The master latch and the slave latch are configured to operate in a first power domain having a first power supply voltage level, the retention latch is configured to operate in a second power domain having a second power supply voltage level different from the first power supply voltage level, and the circuit further includes a level shifter configured to shift a signal level from one of the first power supply voltage level or the second power supply voltage level to the other of the first power supply voltage level or the second power supply voltage level.

公开(公告)号：US12074603B1

公开(公告)日：2024-08-27

申请号：US18313384

申请日：2023-05-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yu-Jheng Ou-Yang ,  Chi-Lin Liu ,  Shang-Chih Hsieh ,  Wei-Hsiang Ma ,  Kai-Chi Huang

IPC: H03K3/037 ,  H03K3/3562

CPC classification number: H03K3/0372 ,  H03K3/0375 ,  H03K3/35625

Abstract: The present disclosure provides a semiconductor device which includes a multiplexer, a master latch, and a slave latch. The multiplexer outputs an inverse of an input data signal or an inverse scan input signal according to a scan enable signal. The master latch is coupled to an output terminal of the multiplexer, and is configured to latch the inverse of the input data signal based on an input clock signal in response to the scan enable signal being in a low-logic state. The slave latch is coupled to the output terminal of the multiplexer through a first clocked CMOS inverter, and is configured to receive the input data signal and to output a latched slave latch data based on the input clock signal. A leakage-free dummy cell is disposed in a non-critical path of the master latch and the slave latch.

公开(公告)号：US11757435B2

公开(公告)日：2023-09-12

申请号：US17815679

申请日：2022-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kai-Chi Huang ,  Yung-Chen Chien ,  Chi-Lin Liu ,  Wei-Hsiang Ma ,  Jerry Chang Jui Kao ,  Shang-Chih Hsieh ,  Lee-Chung Lu

IPC: H03K3/037 ,  G06F1/3237 ,  H03K3/356 ,  H03K19/00

CPC classification number: H03K3/0375 ,  G06F1/3237 ,  H03K3/0372 ,  H03K3/356086 ,  H03K19/0016

Abstract: A circuit includes first and second power nodes having differing first and second voltage levels, and a reference node having a reference voltage level. A master latch outputs a first data bit based on a received data bit; a slave latch includes a first inverter that outputs a second data bit based on the first data bit and a second inverter that outputs an output data bit based on a selected one of the first data bit or a third data bit; a level shifter outputs the third data bit based on a fourth data bit; and a retention latch outputs the fourth data bit based on the second data bit. The first and second inverters and the level shifter are coupled between the first power node and the reference node, and the retention latch includes a plurality of transistors coupled between the second power node and the reference node.

公开(公告)号：US11456728B2

公开(公告)日：2022-09-27

申请号：US17314370

申请日：2021-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kai-Chi Huang ,  Yung-Chen Chien ,  Chi-Lin Liu ,  Wei-Hsiang Ma ,  Jerry Chang Jui Kao ,  Shang-Chih Hsieh ,  Lee-Chung Lu

IPC: H03K3/037 ,  G06F1/3237 ,  H03K19/00 ,  H03K3/356

Abstract: A circuit includes first and second power domains. The first power domain has a first power supply voltage level and includes a master latch, a first level shifter, and a slave latch coupled between the master latch and the first level shifter. The second power domain has a second power supply voltage level different from the first power supply voltage level and includes a retention latch coupled between the slave latch and the first level shifter, and the retention latch includes a second level shifter.