公开(公告)号：US11790145B2

公开(公告)日：2023-10-17

申请号：US17853758

申请日：2022-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Ping Chiang ,  Ming-Hui Chih ,  Chih-Wei Hsu ,  Ping-Chieh Wu ,  Ya-Ting Chang ,  Tsung-Yu Wang ,  Wen-Li Cheng ,  Hui En Yin ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: G06F30/39 ,  G03F1/70 ,  G03F7/20 ,  G03F7/00

CPC classification number: G06F30/39 ,  G03F1/70 ,  G03F7/70466

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

公开(公告)号：US12159092B2

公开(公告)日：2024-12-03

申请号：US18226677

申请日：2023-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Ping Chiang ,  Ming-Hui Chih ,  Chih-Wei Hsu ,  Ping-Chieh Wu ,  Ya-Ting Chang ,  Tsung-Yu Wang ,  Wen-Li Cheng ,  Hui En Yin ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: G06F30/39 ,  G03F1/70 ,  G03F7/00

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

公开(公告)号：US12062540B2

公开(公告)日：2024-08-13

申请号：US17583330

申请日：2022-01-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Ya-Ting Chang ,  Jian-Zhi Huang ,  Jin-Bin Yang ,  I-Chih Ni ,  Chih-I Wu

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/84 ,  H01L23/532 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/02614 ,  H01L21/02568 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/66969 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/786

Abstract: A method for forming an integrated circuit device is provided. The method includes forming a transistor over a frontside of a substrate; forming an interconnect structure over the transistor; depositing a first transition metal layer over the interconnect structure; performing a plasma treatment to turn the first transition metal layer into a first transition metal dichalcogenide layer; forming a dielectric layer over the first transition metal dichalcogenide layer; forming a first gate electrode over the dielectric layer and a first portion of the first transition metal dichalcogenide layer; and forming a first source contact and a first drain contact respectively connected with a second portion and a third portion of the first transition metal dichalcogenide layer, the first portion of the first transition metal dichalcogenide layer being between the second and third portions of the first transition metal dichalcogenide layers.

公开(公告)号：US20140123084A1

公开(公告)日：2014-05-01

申请号：US13666270

申请日：2012-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Po Tang ,  Chih-Shiang Chou ,  Yan-Ting He ,  Ya-Ting Chang ,  Fu-Sheng Chu

IPC: G06F17/50

CPC classification number: G03F7/70441 ,  G03F1/36 ,  G03F7/705 ,  G03F7/70516

Abstract: A method of performing initial optical proximity correction (OPC) with a calibrated lithography simulation model. The method includes providing a photomask having an integrated circuit (IC) pattern formed thereon, acquiring an aerial image of the IC pattern formed on the photomask using an optical microscope, and calibrating an optical component of the lithography simulation model based on the aerial image. The method also includes exposing and developing a photoresist layer on a semiconductor wafer using the photomask to form a post-development pattern on the photoresist layer, acquiring a post-development image of the post-development pattern on the photoresist layer, and calibrating the photoresist component of the lithography simulation model based on the post-development image. Further, the method includes performing initial optical proximity correction (OPC) on an IC design layout based on a simulation of the IC design layout by the lithography simulation model including the calibrated optical and photoresist components.

Abstract translation: 用校准光刻仿真模型执行初始光学邻近校正（OPC）的方法。 该方法包括提供其上形成有集成电路（IC）图案的光掩模，使用光学显微镜获取形成在光掩模上的IC图案的空间图像，并且基于空中图像校准光刻模拟模型的光学部件。 该方法还包括使用光掩模在半导体晶片上曝光和显影光致抗蚀剂层，以在光致抗蚀剂层上形成后显影图案，获得光致抗蚀剂层上后显影图案的显影后图像，并校准光致抗蚀剂 基于后期图像的光刻仿真模型的组成部分。 此外，该方法包括基于通过包括校准的光学和光致抗蚀剂组件的光刻模拟模型对IC设计布局进行的模拟，在IC设计布局上执行初始光学邻近校正（OPC）。