-
公开(公告)号：US11862562B2
公开(公告)日：2024-01-02
申请号：US17459756
申请日：2021-08-27
发明人： Chih-Yu Lai , Hui-Zhong Zhuang , Chih-Liang Chen , Li-Chun Tien
IPC分类号： H01L23/528 , H01L29/417 , H01L21/8238 , H01L23/522 , H01L27/092 , H01L23/552
CPC分类号： H01L23/5286 , H01L21/823871 , H01L23/5226 , H01L23/552 , H01L27/092 , H01L29/41725
摘要： A circuit structure includes a substrate that includes a first transistor stack over the substrate that includes: a first transistor where the first transistor is a first conductivity type; and a second transistor, above the first transistor, where the second transistor is a second conductivity type different from the first conductivity type. The structure also includes a plurality of first conductive lines in a first metal layer above the first transistor stack, the plurality of first conductive lines electrically connected to the first transistor stack. The structure also includes a plurality of second conductive lines in a second metal layer below the substrate and underneath the first transistor stack, the plurality of second conductive lines electrically connected to the first transistor stack. The plurality of first conductive lines are configured asymmetrically with respect to the plurality of second conductive lines.
-
公开(公告)号：US10170539B2
公开(公告)日：2019-01-01
申请号：US15861435
申请日：2018-01-03
发明人： Szu-Yu Wang , Yeur-Luen Tu , Chih-Yu Lai
IPC分类号： H01L49/02 , H01L23/522
摘要： A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a stacked structure and contact vias. The stacked structure includes a plurality of conductive layers, and two adjacent conductive layers are isolated from each other with at least one dielectric layer. The contact vias have different heights, and partially through the stacked structure. Each of the plurality of contact vias is electrically connected to a corresponding conductive layer.
-
公开(公告)号：US20170062496A1
公开(公告)日：2017-03-02
申请号：US14837795
申请日：2015-08-27
IPC分类号： H01L27/146
CPC分类号： H01L27/1463 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/1464 , H01L27/14645 , H01L27/14687 , H01L27/14689 , H01L27/14698
摘要： An embodiment isolation structure includes a first passivation layer over a bottom surface and extending along sidewalls of a trench in a semiconductor substrate, wherein the first passivation layer includes a first dielectric material. The semiconductor device further includes a passivation oxide layer in the trench on the first passivation layer, wherein the passivation oxide layer includes an oxide of the first dielectric material and has a higher atomic percentage of oxygen than the first passivation layer, The semiconductor device further includes a second passivation layer in the trench on the passivation oxide layer, wherein the second passivation layer also includes the first dielectric material and has a lower atomic percentage of oxygen than the passivation oxide layer.
摘要翻译： 实施例的隔离结构包括在底表面上并沿着半导体衬底中的沟槽的侧壁延伸的第一钝化层，其中第一钝化层包括第一介电材料。 所述半导体器件还包括在所述第一钝化层上的所述沟槽中的钝化氧化物层，其中所述钝化氧化物层包括所述第一介电材料的氧化物并且具有比所述第一钝化层更高的原子百分比的氧。所述半导体器件还包括 在所述钝化氧化物层上的所述沟槽中的第二钝化层，其中所述第二钝化层还包括所述第一介电材料并且具有比所述钝化氧化物层低的原子百分比的氧。
-
公开(公告)号：US10163949B2
公开(公告)日：2018-12-25
申请号：US15072887
申请日：2016-03-17
发明人： Chih-Yu Lai , Min-Ying Tsai , Yeur-Luen Tu , Hai-Dang Trinh , Cheng-Yuan Tsai
IPC分类号： H01L27/146
摘要： An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.
-
公开(公告)号：US09871095B2
公开(公告)日：2018-01-16
申请号：US15072936
申请日：2016-03-17
发明人： Szu-Yu Wang , Yeur-Luen Tu , Chih-Yu Lai
IPC分类号： H01L49/02 , H01L23/522
CPC分类号： H01L28/60 , H01L23/5223 , H01L23/5226
摘要： A semiconductor device and method of manufacturing the same is provided. The semiconductor device includes a semiconductor substrate and a stacked capacitor. The stacked capacitor is over the semiconductor substrate. The stacked capacitor includes a lower electrode plate, an upper electrode plate, a dielectric layer, a cap layer, a first via hole and a second via hole. The lower electrode plate is over the semiconductor substrate. The upper electrode plate is over the lower electrode plate. The dielectric layer is between the lower electrode plate and the upper electrode plate. The cap layer is over the upper electrode plate. The first via hole is through the cap layer, the upper electrode plate and the dielectric layer, partially exposing the lower electrode plate. The second via hole is through the cap layer, partially exposing the upper electrode plate.
-
公开(公告)号：US20170373117A1
公开(公告)日：2017-12-28
申请号：US15688351
申请日：2017-08-28
发明人： Cheng-Hsien Chou , Chih-Yu Lai , Shih Pei Chou , Yen-Ting Chiang , Hsiao-Hui Tseng , Min-Ying Tsai
IPC分类号： H01L27/146 , H01L21/762 , H01L29/06
CPC分类号： H01L27/14687 , H01L21/76229 , H01L27/1463 , H01L29/0653
摘要： A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
-
公开(公告)号：US09754993B2
公开(公告)日：2017-09-05
申请号：US14840944
申请日：2015-08-31
发明人： Cheng-Hsien Chou , Hsiao-Hui Tseng , Chih-Yu Lai , Shih Pei Chou , Yen-Ting Chiang , Min-Ying Tsai
IPC分类号： H01L21/762 , H01L27/146 , H01L29/06
CPC分类号： H01L27/14687 , H01L21/76205 , H01L21/76224 , H01L21/76229 , H01L21/76232 , H01L27/1463 , H01L29/0653
摘要： A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
-
公开(公告)号：US09355964B2
公开(公告)日：2016-05-31
申请号：US14203242
申请日：2014-03-10
发明人： Cheng-Hsien Chou , Sheng-Chau Chen , Chun-Wei Chang , Kai-Chun Hsu , Chih-Yu Lai , Wei-Cheng Hsu , Hsiao-Hui Tseng , Shih Pei Chou , Shyh-Fann Ting , Tzu-Hsuan Hsu , Ching-Chun Wang , Yeur-Luen Tu , Dun-Nian Yaung
IPC分类号： H01L21/78 , H01L23/544 , H01L21/762
CPC分类号： H01L23/544 , H01L21/02164 , H01L21/02233 , H01L21/308 , H01L21/7621 , H01L21/76224 , H01L27/1463 , H01L27/14632 , H01L27/14687 , H01L29/0649 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
摘要翻译： 介绍了一种制造非STI CMOS图像传感器对准标记的方法。 在一些实施例中，可以在晶片上同时形成零层对准标记和活性物质对准标记。 可以将晶片的衬底图案化以在衬底中形成一个或多个凹槽。 可以使用例如场氧化方法和/或合适的沉积方法用电介质材料填充凹部。 通过上述过程形成的结构可以对应于零层对准标记的元素和/或对应于有源区对准标记的元件。
-
公开(公告)号：US11854940B2
公开(公告)日：2023-12-26
申请号：US17231527
申请日：2021-04-15
发明人： Chih-Yu Lai , Chih-Liang Chen , Chi-Yu Lu , Shang-Syuan Ciou , Hui-Zhong Zhuang , Ching-Wei Tsai , Shang-Wen Chang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76897 , H01L21/76898
摘要： A semiconductor device includes a substrate and a first transistor on a first side of the substrate. The semiconductor device further includes a first electrode contacting a first region of the first transistor. The semiconductor device further includes a spacer extending along a sidewall of the first transistor. The semiconductor device further includes a self-aligned interconnect structure (SIS) separated from at least a portion of the first electrode by the spacer, wherein the SIS extends through the substrate. The semiconductor device further includes a second electrode contacting a surface of the first electrode farthest from the substrate, wherein the second electrode directly contacts the SIS.
-
公开(公告)号：US11101307B2
公开(公告)日：2021-08-24
申请号：US16202777
申请日：2018-11-28
发明人： Chih-Yu Lai , Min-Ying Tsai , Yeur-Luen Tu , Hai-Dang Trinh , Cheng-Yuan Tsai
IPC分类号： H01L27/146
摘要： An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.
-
-
-
-
-
-
-
-
-
搜索结果
27 条记录 (耗时 0.023 秒)
