公开(公告)号：US20040147116A1

公开(公告)日：2004-07-29

申请号：US10353421

申请日：2003-01-29

Applicant: Taiwan Semiconductor Manufacturing Company

Inventor： Kei-Wei Chen ,  Ting-Chun Wang ,  Kuo-Hsiu Wei ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC: H01L021/00 ,  H01L021/44

CPC classification number: B24B37/0056 ,  B24B37/042 ,  B24B49/02 ,  H01L21/3212 ,  H01L21/7684

Abstract: A new method is provided for polishing, using methods of Chemical Mechanical Polishing, of copper surfaces, particularly where these surface are adjacent to the surface of a layer of barrier material comprising TaN. The invention provides for reducing the chemical force early in the polishing process by adding DIW during the early polishing phase and for additional control of the chemical force during the polishing process by controlling the pH of the slurry applied during polishing, especially for polishing the interface between interconnect copper and barrier material TaN.

Abstract translation: 提供了使用化学机械抛光方法对铜表面进行抛光的新方法，特别是在这些表面与包含TaN的阻挡材料层的表面相邻的地方。 本发明提供了通过在抛光阶段期间添加DIW来在抛光过程中早期降低化学力，并且通过控制在抛光过程中施加的浆料的pH，特别是用于抛光在抛光过程中的界面 互连铜和阻挡材料TaN。

公开(公告)号：US20020090745A1

公开(公告)日：2002-07-11

申请号：US09818962

申请日：2001-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY

Inventor： Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

IPC: H01L021/66 ,  G03C005/00 ,  H01L021/302 ,  H01L021/461 ,  H01L021/311 ,  H01L021/027 ,  H01L021/365 ,  H01L021/443 ,  G03F007/00

CPC classification number: B24B37/013 ,  B24B37/042 ,  B24B49/12 ,  H01L21/31053 ,  H01L21/76224

Abstract: A simple method for calculating the optimum amount of HDP deposited material that needs to be removed during CMP (without introducing dishing) is described. This method derives from our observation of a linear relationship between the amount of material that needs to be removed in order to achieve full planarization and a quantity called nullOD for CMP densitynull. The latter is defined as PAnull(100nullPS) where PA is the percentage of active area relative to the total wafer area and PS is the percentage of sub-areas relative to the total wafer area. The sub-areas are regions in the dielectric, above the active areas, that are etched out prior to CMP. Thus, once the materials have been characterized, the optimum CMP removal thickness is readily calculated for a wide range of different circuit implementations.

Abstract translation: 描述了一种用于计算在CMP期间需要去除的HDP沉积材料的最佳量的简单方法（不引入凹陷）。 该方法来源于我们观察到需要去除的材料的量之间的线性关系以实现完全平坦化，并且称为“用于CMP密度的OD”。 后者被定义为PAx（100-PS），其中PA是相对于总晶片面积的有效面积的百分比，PS是相对于总晶片面积的子区域的百分比。 子区域是在CMP之前被蚀刻出的有源区域之上的电介质区域。 因此，一旦材料被表征，就可以很容易地计算各种不同电路实现的最佳CMP去除厚度。