公开(公告)号：US07859632B2

公开(公告)日：2010-12-28

申请号：US12027748

申请日：2008-02-07

申请人： Sung-Woon Kim ,  Se-Hwan Yu ,  Sung-Tae Shin ,  Hee-Seop Kim

发明人： Sung-Woon Kim ,  Se-Hwan Yu ,  Sung-Tae Shin ,  Hee-Seop Kim

IPC分类号： G02F1/1343 ,  C09K19/02

CPC分类号： G02F1/134363 ,  G02F1/1323 ,  G02F2001/134345 ,  G02F2201/52

摘要： A display device includes a first substrate, a second substrate facing the first substrate, first to third electrodes formed on the first substrate, and a fourth electrode formed on the second substrate, wherein the first and second substrates include a main display region and an assistance display region, wherein the first and second electrodes form a horizontal electric field that is substantially parallel to the surfaces of the first and the second insulating substrates, and the third and fourth electrodes form a vertical electric field that is substantially perpendicular to the surfaces of the first and second substrates.

摘要翻译： 显示装置包括第一基板，面对第一基板的第二基板，形成在第一基板上的第一至第三电极以及形成在第二基板上的第四电极，其中第一和第二基板包括主显示区域和辅助 显示区域，其中所述第一和第二电极形成基本上平行于所述第一和第二绝缘基板的表面的水平电场，并且所述第三和第四电极形成基本上垂直于所述第一和第二绝缘基板的表面的垂直电场 第一和第二基板。

公开(公告)号：US20080273134A1

公开(公告)日：2008-11-06

申请号：US12027748

申请日：2008-02-07

申请人： Sung-Woon KIM ,  Se-Hwan Yu ,  Sung-Tae Shin ,  Hee-Seop Kim

发明人： Sung-Woon KIM ,  Se-Hwan Yu ,  Sung-Tae Shin ,  Hee-Seop Kim

IPC分类号： G02F1/133 ,  G02F1/1335 ,  G02F1/1368

CPC分类号： G02F1/134363 ,  G02F1/1323 ,  G02F2001/134345 ,  G02F2201/52

摘要： A display device includes a first substrate, a second substrate facing the first substrate, first to third electrodes formed on the first substrate, and a fourth electrode formed on the second substrate, wherein the first and second substrates include a main display region and an assistance display region, wherein the first and second electrodes form a horizontal electric field that is substantially parallel to the surfaces of the first and the second insulating substrates, and the third and fourth electrodes form a vertical electric field that is substantially perpendicular to the surfaces of the first and second substrates.

摘要翻译： 显示装置包括第一基板，面对第一基板的第二基板，形成在第一基板上的第一至第三电极以及形成在第二基板上的第四电极，其中第一和第二基板包括主显示区域和辅助 显示区域，其中所述第一和第二电极形成基本上平行于所述第一和第二绝缘基板的表面的水平电场，并且所述第三和第四电极形成基本上垂直于所述第一和第二绝缘基板的表面的垂直电场 第一和第二基板。

公开(公告)号：US09025118B2

公开(公告)日：2015-05-05

申请号：US13619120

申请日：2012-09-14

申请人： Jung-Kyu Lee ,  Yoon-Ho Khang ,  Se-Hwan Yu ,  Cheol-Kyu Kim ,  Yong-Su Lee ,  Chong-Sup Chang ,  Sang-Ho Park ,  Su-Hyoung Kang ,  Hyun-Jae Na ,  Young-Ki Shin

发明人： Jung-Kyu Lee ,  Yoon-Ho Khang ,  Se-Hwan Yu ,  Cheol-Kyu Kim ,  Yong-Su Lee ,  Chong-Sup Chang ,  Sang-Ho Park ,  Su-Hyoung Kang ,  Hyun-Jae Na ,  Young-Ki Shin

IPC分类号： G02F1/136 ,  H01L27/12 ,  G02F1/1362

CPC分类号： H01L27/124 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L27/1288

摘要： A display substrate includes a base substrate, a switching element, a gate line, a data line and a pixel electrode. Each of the gate line and the data line includes a first metal layer, and a second metal layer directly on the first metal layer. The switching element is on the base substrate, and includes a control electrode and an input electrode or an output electrode. The control electrode includes the first metal layer and excludes the second metal layer, and extends from the gate line. The input electrode or the output electrode includes a second metal layer and excludes the first metal layer. The input electrode extends from the data line. The pixel electrode is electrically connected to the output electrode of the switching element through a first contact hole, and includes a transparent conductive layer.

摘要翻译： 显示基板包括基底基板，开关元件，栅极线，数据线和像素电极。 栅极线和数据线中的每一个包括第一金属层和直接在第一金属层上的第二金属层。 开关元件在基底基板上，并且包括控制电极和输入电极或输出电极。 控制电极包括第一金属层，并且不包括第二金属层，并且从栅极线延伸。 输入电极或输出电极包括第二金属层，并且不包括第一金属层。 输入电极从数据线延伸。 像素电极通过第一接触孔电连接到开关元件的输出电极，并且包括透明导电层。

公开(公告)号：US08721905B2

公开(公告)日：2014-05-13

申请号：US13431516

申请日：2012-03-27

申请人： Se-Hwan Yu ,  Ji Seon Lee ,  Yoon Ho Khang ,  Kahp Yang Suh ,  Hyoung Sick Um ,  Jae Jun Chae ,  Sung Hun Lee

发明人： Se-Hwan Yu ,  Ji Seon Lee ,  Yoon Ho Khang ,  Kahp Yang Suh ,  Hyoung Sick Um ,  Jae Jun Chae ,  Sung Hun Lee

IPC分类号： H01L21/302

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00

摘要： A method for forming a minute pattern mask includes forming an etching target layer on a substrate. A convex pattern including a plurality of convex parts is formed on the etching target layer. A resin composition is coated on the convex pattern to form a resin layer including a first region neighboring the convex part and a second region positioned between the neighboring convex parts. The resin layer is ashed or etched to form the plurality of first resin patterns. The plurality of first resin patterns is processed to form a minute pattern mask including a plurality of second resin patterns. The etching target layer is etched using the plurality of second resin patterns as an etch mask to form a minute pattern.

摘要翻译： 形成微图案掩模的方法包括在基板上形成蚀刻目标层。 在蚀刻目标层上形成包括多个凸部的凸形图案。 将树脂组合物涂覆在凸形图案上以形成包括邻近凸部的第一区域和位于相邻凸部之间的第二区域的树脂层。 树脂层被灰化或蚀刻以形成多个第一树脂图案。 处理多个第一树脂图案以形成包括多个第二树脂图案的微小图案掩模。 使用多个第二树脂图案作为蚀刻掩模蚀刻蚀刻目标层以形成微小图案。

公开(公告)号：US20130105826A1

公开(公告)日：2013-05-02

申请号：US13619120

申请日：2012-09-14

申请人： Jung-Kyu Lee ,  Yoon-Ho Khang ,  Se-Hwan Yu ,  Cheol-Kyu Kim ,  Yong-Su Lee ,  Chong-Sup Chang ,  Sang-Ho Park ,  Su-Hyoung Kang ,  Hyun-Jae Na ,  Young-Ki Shin

发明人： Jung-Kyu Lee ,  Yoon-Ho Khang ,  Se-Hwan Yu ,  Cheol-Kyu Kim ,  Yong-Su Lee ,  Chong-Sup Chang ,  Sang-Ho Park ,  Su-Hyoung Kang ,  Hyun-Jae Na ,  Young-Ki Shin

IPC分类号： H01L33/08

CPC分类号： H01L27/124 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L27/1288

摘要： A display substrate includes a base substrate, a switching element, a gate line, a data line and a pixel electrode. Each of the gate line and the data line includes a first metal layer, and a second metal layer directly on the first metal layer. The switching element is on the base substrate, and includes a control electrode and an input electrode or an output electrode. The control electrode includes the first metal layer and excludes the second metal layer, and extends from the gate line. The input electrode or the output electrode includes a second metal layer and excludes the first metal layer. The input electrode extends from the data line. The pixel electrode is electrically connected to the output electrode of the switching element through a first contact hole, and includes a transparent conductive layer.

摘要翻译： 显示基板包括基底基板，开关元件，栅极线，数据线和像素电极。 栅极线和数据线中的每一个包括第一金属层和直接在第一金属层上的第二金属层。 开关元件在基底基板上，并且包括控制电极和输入电极或输出电极。 控制电极包括第一金属层，并且不包括第二金属层，并且从栅极线延伸。 输入电极或输出电极包括第二金属层，并且不包括第一金属层。 输入电极从数据线延伸。 像素电极通过第一接触孔电连接到开关元件的输出电极，并且包括透明导电层。

公开(公告)号：US07459323B2

公开(公告)日：2008-12-02

申请号：US11512805

申请日：2006-08-30

申请人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

发明人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC分类号： H01L21/00

CPC分类号： G02F1/1368 ,  G02F1/1339

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20130098869A1

公开(公告)日：2013-04-25

申请号：US13431516

申请日：2012-03-27

申请人： Se-Hwan Yu ,  Ji Seon Lee ,  Yoon Ho Khang ,  Kahp Yang Suh ,  Hyoung Sick Um ,  Jae Jun Chae ,  Sung Hun Lee

发明人： Se-Hwan Yu ,  Ji Seon Lee ,  Yoon Ho Khang ,  Kahp Yang Suh ,  Hyoung Sick Um ,  Jae Jun Chae ,  Sung Hun Lee

IPC分类号： B44C1/22

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00

摘要： A method for forming a minute pattern mask includes forming an etching target layer on a substrate. A convex pattern including a plurality of convex parts is formed on the etching target layer. A resin composition is coated on the convex pattern to form a resin layer including a first region neighboring the convex part and a second region positioned between the neighboring convex parts. The resin layer is ashed or etched to form the plurality of first resin patterns. The plurality of first resin patterns is processed to form a minute pattern mask including a plurality of second resin patterns. The etching target layer is etched using the plurality of second resin patterns as an etch mask to form a minute pattern.

摘要翻译： 形成微图案掩模的方法包括在基板上形成蚀刻目标层。 在蚀刻目标层上形成包括多个凸部的凸形图案。 将树脂组合物涂覆在凸形图案上以形成包括邻近凸部的第一区域和位于相邻凸部之间的第二区域的树脂层。 树脂层被灰化或蚀刻以形成多个第一树脂图案。 处理多个第一树脂图案以形成包括多个第二树脂图案的微小图案掩模。 使用多个第二树脂图案作为蚀刻掩模蚀刻蚀刻目标层以形成微小图案。

公开(公告)号：US08427623B2

公开(公告)日：2013-04-23

申请号：US12816591

申请日：2010-06-16

申请人： Se-Hwan Yu ,  Hyang-Shik Kong ,  Su-Hyoung Kang

发明人： Se-Hwan Yu ,  Hyang-Shik Kong ,  Su-Hyoung Kang

IPC分类号： G02F1/1333 ,  G02F1/1343 ,  G02F1/1345

CPC分类号： G02F1/136286 ,  G02F2001/13629

摘要： A thin film transistor array panel including a display area having a gate line, a data line insulated from and intersecting the gate line, a thin film transistor connected to the gate line and the data line, and a pixel electrode connected to the thin film transistor, and a peripheral area formed on the circumference of the display area, according to an exemplary embodiment of the present invention, includes: a driving signal line formed with the same layer as the gate line in the peripheral area and receiving an external signal; a connection signal line formed with the same layer as the data line in the peripheral area; a disconnection prevention member overlapping the side surface of the connection signal line on the connection signal line; and a connection assistance member formed on the disconnection prevention member and connecting the driving signal line and the connection signal line.

摘要翻译： 一种薄膜晶体管阵列面板，包括具有栅极线的显示区域，与栅极线绝缘并与之相交的数据线，连接到栅极线和数据线的薄膜晶体管，以及连接到薄膜晶体管的像素电极 以及形成在显示区域的圆周上的周边区域，根据本发明的示例性实施例，包括：形成与周边区域中的栅极线相同层并且接收外部信号的驱动信号线; 连接信号线，其与周边区域中的数据线形成相同的层; 断开防止部件与连接信号线上的连接信号线的侧面重叠; 以及连接辅助构件，其形成在所述防止断开构件上并且连接所述驱动信号线和所述连接信号线。

公开(公告)号：US07119368B2

公开(公告)日：2006-10-10

申请号：US10926719

申请日：2004-08-26

申请人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

发明人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC分类号： H01L31/0376

CPC分类号： G02F1/1368 ,  G02F1/1339

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

公开(公告)号：US07023016B2

公开(公告)日：2006-04-04

申请号：US10884083

申请日：2004-07-01

申请人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

发明人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC分类号： H01L29/04

CPC分类号： H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.