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1.发明申请公开(公告)号：US20120311364A1
公开(公告)日：2012-12-06
申请号：US13587048
申请日：2012-08-16
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3293 , Y02D10/122 , Y02D50/20
摘要： An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.
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2.发明申请Information Handling System with Processing System, Low-power Processing System and Shared Resources 有权具有处理系统，低功耗处理系统和共享资源的信息处理系统公开(公告)号：US20120013795A1
公开(公告)日：2012-01-19
申请号：US13242635
申请日：2011-09-23
CPC分类号： G06F1/3203 , G06F1/3293 , Y02D10/122 , Y02D50/20
摘要： An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.
摘要翻译： 信息处理系统包括处理系统，低功率处理系统和芯片组。 处理系统被配置为使用被配置为为处理系统的共享资源和处理系统的非共享资源供电的电力系统来操作，并且在处理系统的减少的操作状态期间禁用非共享资源。 低功率处理系统被配置为在低功率处理系统的操作期间访问处理系统的共享资源，其中低功率处理系统的操作与处理系统的操作分离。 芯片组包括处理系统的处理器，并且可操作以在处理系统的操作期间启用，其中处理器被配置为在低功率处理系统的操作期间被禁用。
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3.发明授权Information handling system with processing system, low-power processing system and shared resources 有权具有处理系统，低功耗处理系统和共享资源的信息处理系统公开(公告)号：US08799695B2
公开(公告)日：2014-08-05
申请号：US13587048
申请日：2012-08-16
CPC分类号： G06F1/3203 , G06F1/3293 , Y02D10/122 , Y02D50/20
摘要： An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.
摘要翻译： 信息处理系统包括处理系统，低功率处理系统和芯片组。 处理系统被配置为使用被配置为为处理系统的共享资源和处理系统的非共享资源供电的电力系统来操作，并且在处理系统的减少的操作状态期间禁用非共享资源。 低功率处理系统被配置为在低功率处理系统的操作期间访问处理系统的共享资源，其中低功率处理系统的操作与处理系统的操作分离。 芯片组包括处理系统的处理器，并且可操作以在处理系统的操作期间启用，其中处理器被配置为在低功率处理系统的操作期间被禁用。
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4.发明授权Information handling system with processing system, low-power processing system and shared resources 有权具有处理系统，低功耗处理系统和共享资源的信息处理系统公开(公告)号：US08271817B2
公开(公告)日：2012-09-18
申请号：US13242635
申请日：2011-09-23
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3293 , Y02D10/122 , Y02D50/20
摘要： An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.
摘要翻译： 信息处理系统包括处理系统，低功率处理系统和芯片组。 处理系统被配置为使用被配置为为处理系统的共享资源和处理系统的非共享资源供电的电力系统来操作，并且在处理系统的减少的操作状态期间禁用非共享资源。 低功率处理系统被配置为在低功率处理系统的操作期间访问处理系统的共享资源，其中低功率处理系统的操作与处理系统的操作分离。 芯片组包括处理系统的处理器，并且可操作以在处理系统的操作期间启用，其中处理器被配置为在低功率处理系统的操作期间被禁用。
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5.发明授权Information handling system with processing system, low-power processing system and shared resources 有权具有处理系统，低功耗处理系统和共享资源的信息处理系统公开(公告)号：US08037333B2
公开(公告)日：2011-10-11
申请号：US12262965
申请日：2008-10-31
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3293 , Y02D10/122 , Y02D50/20
摘要： An information handling system employs low-power processing. In a particular form, an information handling system can include a processing system configured operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system. The information handling system can also include a low-power processing system configured to access the shared resource of the processing system during operation of the low-power processing system. The operation of the low-power processing system can be separate from the operation of the processing system. The information handling system can also include a chipset including a processor of the processing system and operable to be enabled during operation of the processing system. The processor can be configured to be disabled during operation of the low-power processing system.
摘要翻译： 信息处理系统采用低功耗处理。 在特定形式中，信息处理系统可以包括配置的处理系统，其使用被配置为为处理系统的共享资源和处理系统的非共享资源供电的电力系统。 信息处理系统还可以包括配置为在低功率处理系统的操作期间访问处理系统的共享资源的低功率处理系统。 低功率处理系统的操作可以与处理系统的操作分开。 信息处理系统还可以包括包括处理系统的处理器并且可操作以在处理系统的操作期间被启用的芯片组。 处理器可以配置为在低功耗处理系统的运行期间被禁用。
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6.发明申请公开(公告)号：US20100115313A1
公开(公告)日：2010-05-06
申请号：US12262965
申请日：2008-10-31
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3293 , Y02D10/122 , Y02D50/20
摘要： An information handling system employs low-power processing. In a particular form, an information handling system can include a processing system configured operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system. The information handling system can also include a low-power processing system configured to access the shared resource of the processing system during operation of the low-power processing system. The operation of the low-power processing system can be separate from the operation of the processing system. The information handling system can also include a chipset including a processor of the processing system and operable to be enabled during operation of the processing system. The processor can be configured to be disabled during operation of the low-power processing system.
摘要翻译： 信息处理系统采用低功耗处理。 在特定形式中，信息处理系统可以包括配置的处理系统，其使用被配置为为处理系统的共享资源和处理系统的非共享资源供电的电力系统。 信息处理系统还可以包括配置为在低功率处理系统的操作期间访问处理系统的共享资源的低功率处理系统。 低功率处理系统的操作可以与处理系统的操作分开。 信息处理系统还可以包括包括处理系统的处理器并且可操作以在处理系统的操作期间被启用的芯片组。 处理器可以配置为在低功耗处理系统的运行期间被禁用。
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7.发明授权Microprocessor including an interrupt polling unit configured to poll external devices for interrupts using interrupt acknowledge bus transactions 失效微处理器包括一个中断轮询单元，配置为使用中断确认总线事务轮询外部设备进行中断
公开(公告)号：US5687381A
公开(公告)日：1997-11-11
申请号：US599603
申请日：1996-02-09
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： An interrupt polling unit included within a bus interface unit of a microprocessor is provided. The interrupt polling unit causes a periodic interrupt acknowledge bus transaction to occur. If an interrupt controller receiving the interrupt acknowledge bus transaction returns an interrupt vector indicative of an interrupt service routine, then the microprocessor executes the interrupt service routine. The number of interrupt acknowledge bus transactions associated with the interrupt is reduced from two to one, and the microprocessor effectively prefetches the interrupt service routine before the interrupt is actually signaled. In one embodiment, the interrupt polling unit causes an interrupt acknowledge bus transaction to occur at the expiration of a programmable time interval. Another embodiment of the interrupt polling unit causes an interrupt acknowledge bus transaction subsequent to the occurrence of a bus transaction programmed by the user.
摘要翻译： 提供了包括在微处理器的总线接口单元内的中断轮询单元。 中断轮询单元导致周期性中断确认总线事务发生。 如果接收到中断确认总线事务的中断控制器返回指示中断服务程序的中断向量，则微处理器执行中断服务程序。 与中断相关联的中断确认总线事务数量从两个减少到一个，并且微处理器在实际发出中断之前有效地预取中断服务程序。 在一个实施例中，中断轮询单元导致在可编程时间间隔期满时发生中断确认总线事务。 中断轮询单元的另一实施例在由用户编程的总线事务发生之后导致中断确认总线事务。
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8.发明授权Apparatus for maintaining one interrupt mask register in conformity with another in a manner invisible to an executing program 失效用于以一种执行程序不可见的方式维持一个中断屏蔽寄存器与另一个中断屏蔽寄存器一致的装置
公开(公告)号：US5551033A
公开(公告)日：1996-08-27
申请号：US893432
申请日：1992-06-04
申请人： Mark J. Foster , Saifuddin T. Fakhruddin , James L. Walker , Matthew B. Mendelow , Jiming Sun , Rodman S. Brahman , Michael P. Krau , Brian D. Willoughby , Michael D. Maddix , Steven L. Belt , Scott A. Hovey , Mark A. Ruthenbeck
发明人： Mark J. Foster , Saifuddin T. Fakhruddin , James L. Walker , Matthew B. Mendelow , Jiming Sun , Rodman S. Brahman , Michael P. Krau , Brian D. Willoughby , Michael D. Maddix , Steven L. Belt , Scott A. Hovey , Mark A. Ruthenbeck
CPC分类号： G06F9/4812 , G06F1/24 , G06F1/3203 , G06F1/324 , G06F9/463 , Y02B60/1217 , Y02B60/144
摘要： A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. The system includes a first interrupt mask register having a bit for indicating whether an interrupt is to be recognized by the processor, a second interrupt mask register having a bit for indicating whether the interrupt is to be recognized by a further circuit, and an arrangement responsive to a load of the first mask register for conforming the bit of the second mask register to the bit of the first mask register in a manner invisible to an application program being executed by the processor.
摘要翻译： 膝上型计算机系统包括能够以受限制和无限制模式操作的保护模式微处理器，并且响应于预定条件的装置保存来自处理器的信息，然后强制地将处理器切换到其无限制操作模式。 该系统包括第一中断屏蔽寄存器，该第一中断屏蔽寄存器具有用于指示处理器是否识别中断的位;第二中断屏蔽寄存器，具有用于指示该中断是否被另一电路识别的位，以及响应于 到第一掩模寄存器的负载，用于使第二掩模寄存器的位与第一掩模寄存器的位以对于由处理器执行的应用程序不可见的方式进行匹配。
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公开(公告)号：US5754190A
公开(公告)日：1998-05-19
申请号：US481630
申请日：1995-06-07
CPC分类号： G06T9/001
摘要： A method and apparatus for transferring original data which includes images, between two stations located a distance apart, without actual transmission of the image portion of the data. A library of images are provided at each of the stations. The image to be transferred is processed into a description of the image which allows the reproduction of the image at the receiving end of the transmission using the images contained in the image library in the receiving station.
摘要翻译： 一种用于传送原始数据的方法和装置，其中包括位于距离分开的两个站之间的图像，而不实际传输数据的图像部分。 每个电台都提供图像库。 要传送的图像被处理成图像的描述，其允许使用包含在接收站中的图像库中的图像在传输的接收端再现图像。
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公开(公告)号：US5446904A
公开(公告)日：1995-08-29
申请号：US894511
申请日：1992-06-04
申请人： Steven L. Belt , Scott A. Hovey
发明人： Steven L. Belt , Scott A. Hovey
CPC分类号： G06F9/4812 , G06F1/24 , G06F1/3203 , G06F1/324 , G06F9/463 , Y02B60/1217 , Y02B60/144
摘要： A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. When running a multi-tasking operating system where an application program is being executed in a restricted mode, a suspend/resume operation can be carried out in which the system is substantially powered down and then powered back up, and will resume the interrupted application with the restricted mode back-in effect. Further, set-up changes such as adjustment of the processor speed can be made without exiting the application program running in the restricted mode.
摘要翻译： 膝上型计算机系统包括能够以受限制和无限制模式操作的保护模式微处理器，并且响应于预定条件的装置保存来自处理器的信息，然后强制地将处理器切换到其无限制操作模式。 当在受限制的模式下运行应用程序的多任务操作系统时，可以执行暂停/恢复操作，其中系统基本上断电然后重新上电，并且将以 限制模式后援效果。 此外，可以在不退出在限制模式下运行的应用程序的情况下进行诸如调整处理器速度的设置更改。
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