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    Computer system which performs intelligent byte slicing/data packing on a multi-byte wide bus
    1.
    发明授权
    Computer system which performs intelligent byte slicing/data packing on a multi-byte wide bus 失效
    在多字节宽总线上执行智能字节分片/数据打包的计算机系统

    公开(公告)号：US06061756A

    公开(公告)日：2000-05-09

    申请号：US89025

    申请日：1998-06-02

    申请人： Drew J. Dutton ,  Scott E. Swanstrom ,  J. Andrew Lambrecht

    发明人： Drew J. Dutton ,  Scott E. Swanstrom ,  J. Andrew Lambrecht

    IPC分类号： G06F13/368 ,  G06F13/372 ,  G06F13/40 ,  H04N21/238 ,  G06F13/38

    CPC分类号： H04N21/238 ,  G06F13/368 ,  G06F13/372 ,  G06F13/4013 ,  G06F13/4027

    摘要： A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and may also include a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing and/or data packing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The data packing logic may optimally fill the bus with data having more or fewer bits than the bus. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

    摘要翻译： 针对实时应用程序进行了优化的计算机系统，提高了当前计算机体系结构的性能。 该系统包括标准本地系统总线或扩展总线，例如PCI总线，并且还可以包括专用实时总线或多媒体总线。 各种多媒体设备耦合到一个或多个扩展总线和/或多媒体总线。 计算机系统包括耦合到扩展总线和/或多媒体总线中的一个或多个的字节分片和/或数据打包逻辑，其操作以允许不同的数据流同时使用不同的字节通道。 因此，字节分片总线允许不同的外设同时共享总线。 因此，字节分片逻辑可以将一个数据流分配给多媒体总线上的总字节通道的子集，并且用另一个数据流填充未使用的字节通道。 数据打包逻辑可以使用比总线更多或更少位的数据来最佳地填充总线。 因此，本发明的计算机系统为实时应用提供比现有系统更大的性能。

    Bus arbiter including programmable request latency counters for varying arbitration priority
    2.
    发明授权
    Bus arbiter including programmable request latency counters for varying arbitration priority 失效
    总线仲裁器包括用于改变仲裁优先级的可编程请求延迟计数器

    公开(公告)号：US5956493A

    公开(公告)日：1999-09-21

    申请号：US612535

    申请日：1996-03-08

    申请人： Larry D. Hewitt ,  Scott E. Swanstrom

    发明人： Larry D. Hewitt ,  Scott E. Swanstrom

    IPC分类号： G06F13/364 ,  G06F13/36 ,  G06F13/362

    CPC分类号： G06F13/364

    摘要： A computer system is provided for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership of the bus. A set of counters referred to as "request latency" counters is further provided wherein a separate counter unit corresponds to each bus master. Each counter is configured to generate a signal indicative of a lapse of time since a time when the peripheral requested ownership of the bus. An arbitration control unit is coupled to the request latency counters, the request detection unit and the grant generator for processing incoming bus request signals. The arbitration control unit is configured to dynamically vary the level of arbitration priority given to each peripheral device based upon the latency signal corresponding to the device. Accordingly, as the time from when a peripheral device requests the bus increases, the level of arbitration priority given to that peripheral also increases. A set of programmable registers are provided to allow software programming of the initial count value associated with each request latency counter. The request latency counter for a particular device may further be held or inhibited from counting to provide a constant level of priority for that particular peripheral device.

    摘要翻译： 提供了一种用于控制总线的所有权的计算机系统，多个实时资源和非实时资源耦合到总线。 总线仲裁器包括用于检测多个总线主机的总线请求信号的请求检测单元，以及用于产生相应的授权信号的授权发生器，用于指示总线的所有权授权。 还提供了称为“请求延迟”计数器的一组计数器，其中单独的计数器单元对应于每个总线主机。 每个计数器被配置为产生指示从外围设备请求所有总线的时间起经过的时间的信号。 仲裁控制单元耦合到请求等待时间计数器，请求检测单元和用于处理输入总线请求信号的授权发生器。 仲裁控制单元被配置为基于与设备相对应的等待时间信号来动态地改变给予每个外围设备的仲裁优先级。 因此，随着外围设备请求总线的时间增加，给予该外设的仲裁优先级也增加。 提供一组可编程寄存器以允许与每个请求延迟计数器相关联的初始计数值的软件编程。 特定设备的请求等待时间计数器可进一步被保持或禁止计数，以为该特定外围设备提供恒定的优先级。

    Microprocessor including an interrupt polling unit configured to poll external devices for interrupts using interrupt acknowledge bus transactions
    4.
    发明授权
    Microprocessor including an interrupt polling unit configured to poll external devices for interrupts using interrupt acknowledge bus transactions 失效
    微处理器包括一个中断轮询单元，配置为使用中断确认总线事务轮询外部设备进行中断

    公开(公告)号：US5687381A

    公开(公告)日：1997-11-11

    申请号：US599603

    申请日：1996-02-09

    申请人： Scott E. Swanstrom ,  David S. Christie ,  Steven L. Belt

    发明人： Scott E. Swanstrom ,  David S. Christie ,  Steven L. Belt

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24

    摘要： An interrupt polling unit included within a bus interface unit of a microprocessor is provided. The interrupt polling unit causes a periodic interrupt acknowledge bus transaction to occur. If an interrupt controller receiving the interrupt acknowledge bus transaction returns an interrupt vector indicative of an interrupt service routine, then the microprocessor executes the interrupt service routine. The number of interrupt acknowledge bus transactions associated with the interrupt is reduced from two to one, and the microprocessor effectively prefetches the interrupt service routine before the interrupt is actually signaled. In one embodiment, the interrupt polling unit causes an interrupt acknowledge bus transaction to occur at the expiration of a programmable time interval. Another embodiment of the interrupt polling unit causes an interrupt acknowledge bus transaction subsequent to the occurrence of a bus transaction programmed by the user.

    摘要翻译： 提供了包括在微处理器的总线接口单元内的中断轮询单元。 中断轮询单元导致周期性中断确认总线事务发生。 如果接收到中断确认总线事务的中断控制器返回指示中断服务程序的中断向量，则微处理器执行中断服务程序。 与中断相关联的中断确认总线事务数量从两个减少到一个，并且微处理器在实际发出中断之前有效地预取中断服务程序。 在一个实施例中，中断轮询单元导致在可编程时间间隔期满时发生中断确认总线事务。 中断轮询单元的另一实施例在由用户编程的总线事务发生之后导致中断确认总线事务。

    Microprocessor including an interrupt polling unit configured to poll external devices for interrupts when said microprocessor is in a task switch state
    5.
    发明授权
    Microprocessor including an interrupt polling unit configured to poll external devices for interrupts when said microprocessor is in a task switch state 失效
    微处理器包括一个中断轮询单元，配置为当所述微处理器处于任务切换状态时轮询外部设备进行中断

    公开(公告)号：US5948093A

    公开(公告)日：1999-09-07

    申请号：US599618

    申请日：1996-02-09

    申请人： Scott E. Swanstrom ,  David S. Christie ,  Steven L. Belt

    发明人： Scott E. Swanstrom ,  David S. Christie ,  Steven L. Belt

    IPC分类号： G06F9/32 ,  G06F9/48 ,  G06F9/22

    CPC分类号： G06F9/4812 ,  G06F9/32

    摘要： An interrupt polling unit included within a bus interface unit of a microprocessor is provided. The interrupt polling unit causes an interrupt acknowledge bus transaction to occur. If an interrupt controller receiving the interrupt acknowledge bus transaction returns an interrupt vector indicative of an interrupt service routine, then the microprocessor executes the interrupt service routine. The number of interrupt acknowledge bus transactions associated with the interrupt is reduced from two to one. In one embodiment, the interrupt polling unit causes an interrupt acknowledge bus transaction to occur when the microprocessor is performing a task switch. The task switch may be performed by hardware included within the microprocessor or, alternatively, by software executing upon the microprocessor.

    摘要翻译： 提供了包括在微处理器的总线接口单元内的中断轮询单元。 中断轮询单元导致发生中断确认总线事务。 如果接收到中断确认总线事务的中断控制器返回指示中断服务程序的中断向量，则微处理器执行中断服务程序。 与中断相关联的中断确认总线事务数量从两个减少到一个。 在一个实施例中，当微处理器执行任务切换时，中断轮询单元导致中断确认总线事务发生。 任务切换可以由包括在微处理器内的硬件执行，或者由软件在微处理器上执行。

    Serial interface having a read temperature command
    6.
    发明授权
    Serial interface having a read temperature command 有权
    具有读取温度命令的串行接口

    公开(公告)号：US07231474B1

    公开(公告)日：2007-06-12

    申请号：US11140803

    申请日：2005-05-31

    申请人： Frank P. Helms ,  Larry D. Hewitt ,  Scott E. Swanstrom ,  Ross Voigt LaFetra

    发明人： Frank P. Helms ,  Larry D. Hewitt ,  Scott E. Swanstrom ,  Ross Voigt LaFetra

    IPC分类号： G06F1/30 ,  G06F1/20 ,  G06F13/00

    CPC分类号： G06F1/206

    摘要： A serial communication system includes an integrated circuit having a master serial interface; and a processor having a slave serial interface coupled to the master serial interface through a clock signal line and a data signal line. The slave serial interface is responsive to a read temperature command issued by the master serial interface to return a first temperature value associated with the processor.

    摘要翻译： 串行通信系统包括具有主串行接口的集成电路; 以及具有通过时钟信号线和数据信号线耦合到主串行接口的从串行接口的处理器。 从串行接口响应于由主串行接口发出的读温度命令返回与处理器相关联的第一温度值。

    Independent use of bits on an on-chip bus
    7.
    发明授权
    Independent use of bits on an on-chip bus 失效
    独立使用片上总线上的位

    公开(公告)号：US6035364A

    公开(公告)日：2000-03-07

    申请号：US989330

    申请日：1997-12-11

    申请人： J. Andrew Lambrecht ,  Scott E. Swanstrom

    发明人： J. Andrew Lambrecht ,  Scott E. Swanstrom

    IPC分类号： G06F13/12 ,  G06F13/36 ,  G06F13/368 ,  G06F13/372 ,  G06F13/40 ,  H04N21/238 ,  G06F13/38

    CPC分类号： H04N21/238 ,  G06F13/124 ,  G06F13/36 ,  G06F13/368 ,  G06F13/372 ,  G06F13/4013 ,  G06F13/4022 ,  G06F13/4027

    摘要： A computer chip including multiple on-chip modules connected by an on-chip bus which provides increased performance over current computer chip architectures. The on-chip system bus is a bit sliced bus. Various transmitters/and or receivers are coupled the bit sliced bus. The transmitters and/or receivers include bus interface logic and/or bit transfer logic and/or bit receive logic operatively coupled to the on-chip bit sliced bus which operates to allow different data streams to use different bit lines substantially simultaneously. Thus the bit sliced bus allows different devices to share the bus simultaneously. The bus interface logic and/or the bit transfer logic thus may assign one data stream to a subset of the total bit lines on the bit sliced bus, and fill the unused bit lines with another data stream.

    摘要翻译： 包括通过片上总线连接的多个片上模块的计算机芯片，其提供超过当前计算机芯片架构的性能。 片上系统总线是一个有点切片的总线。 各种发射机和/或接收机与位分片总线耦合。 发射器和/或接收器包括可操作地耦合到片上位分片总线的总线接口逻辑和/或位传输逻辑和/或位接收逻辑，其操作以允许不同的数据流基本上同时使用不同的位线。 因此，位分片总线允许不同的设备同时共享总线。 因此，总线接口逻辑和/或位传输逻辑可以将一个数据流分配给位分片总线上的总位线的子集，并且用另一数据流填充未使用的位线。

    Computer system which performs intelligent byte slicing on a multi-byte wide bus
    10.
    发明授权
    Computer system which performs intelligent byte slicing on a multi-byte wide bus 失效
    在多字节宽总线上执行智能字节分片的计算机系统

    公开(公告)号：US6047350A

    公开(公告)日：2000-04-04

    申请号：US989329

    申请日：1997-12-11

    申请人： Drew J. Dutton ,  Scott E. Swanstrom ,  J. Andrew Lambrecht

    发明人： Drew J. Dutton ,  Scott E. Swanstrom ,  J. Andrew Lambrecht

    IPC分类号： G06F13/36 ,  G06F13/368 ,  G06F13/372 ,  G06F13/40 ,  H04N21/238 ,  G06F13/38

    CPC分类号： H04N21/238 ,  G06F13/36 ,  G06F13/368 ,  G06F13/372 ,  G06F13/4013 ,  G06F13/4022 ,  G06F13/4027

    摘要： A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and may also include a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced multimedia bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

    摘要翻译： 针对实时应用程序进行了优化的计算机系统，提高了当前计算机体系结构的性能。 该系统包括标准本地系统总线或扩展总线，例如PCI总线，并且还可以包括专用实时总线或多媒体总线。 各种多媒体设备耦合到一个或多个扩展总线和/或多媒体总线。 计算机系统包括耦合到一个或多个扩展总线和/或多媒体总线的字节分片逻辑，其操作以允许不同的数据流同时使用不同的字节通道。 因此，字节分片多媒体总线允许不同的外设同时共享总线。 因此，字节分片逻辑可以将一个数据流分配给多媒体总线上的总字节通道的子集，并且用另一个数据流填充未使用的字节通道。 因此，本发明的计算机系统为实时应用提供比现有系统更大的性能。