公开(公告)号：US08305325B2

公开(公告)日：2012-11-06

申请号：US12063306

申请日：2007-03-30

申请人： Somei Kawasaki ,  Masami Iseki ,  Fujio Kawano

发明人： Somei Kawasaki ,  Masami Iseki ,  Fujio Kawano

IPC分类号： G09G3/36

CPC分类号： G09G3/3241 ,  G09G3/3275 ,  G09G2300/0408 ,  G09G2310/0262 ,  G09G2310/027 ,  G09G2310/0297

摘要： A color display apparatus includes a display unit having electro-optical elements arranged in a row direction and a column direction, scanning lines provided in respective rows of the electro-optical elements to select respective rows, and data lines provided in respective columns and supplying data signals to electro-optical elements in the row which the scanning lines select, and conversion circuits each of which receives a digital video signal and converts the digital video signal to an analog video signal. In addition, a first dispersion circuit receives the analog video signals outputted from the conversion circuits and exchanges an arrangement of the analog video signals to output to bus lines, column drive circuits sample the analog video signals in the bus lines in a time sharing manner and generate and output the data signals, and a second dispersion circuit receives the data signals outputted from the column drive circuits and rearranges the data signals to output to the data lines. The rearranging of the data signals by the second dispersion circuit restores the exchanging of the arrangement by the first dispersion circuit.

摘要翻译： 一种彩色显示装置，包括具有排列成行方向和列方向的电光元件的显示单元，设置在电光元件的各行中的扫描线，以选择各行，以及设置在各列中的数据线，并提供数据 信号到扫描线选择的行中的电光元件，以及各自接收数字视频信号并将数字视频信号转换为模拟视频信号的转换电路。 此外，第一色散电路接收从转换电路输出的模拟视频信号并交换模拟视频信号的布置以输出到总线，列驱动电路以时分方式对总线中的模拟视频信号进行采样， 产生并输出数据信号，第二色散电路接收从列驱动电路输出的数据信号，并重新排列数据信号以输出到数据线。 由第二色散电路重新排列数据信号，恢复由第一色散电路进行的配置的交换。

公开(公告)号：US07692643B2

公开(公告)日：2010-04-06

申请号：US11283743

申请日：2005-11-22

申请人： Somei Kawasaki ,  Masami Iseki ,  Fujio Kawano ,  Takanori Yamashita

发明人： Somei Kawasaki ,  Masami Iseki ,  Fujio Kawano ,  Takanori Yamashita

IPC分类号： G06F3/038

CPC分类号： G09G3/325 ,  G09G2300/0842 ,  G09G2310/0248 ,  G09G2320/0223

摘要： An active matrix type display apparatus includes a plurality of pixel circuits each having an electroluminescent element EL, a 1st FET to control a current flowing in the EL, and a 2nd FET provided between a gate and a drain of the 1st FET. The plurality of pixel circuits are arranged in a matrix and have every column connected to a data line. The 2nd FET is turned on for a predetermined time period, and an image data current flowing in the data line is supplied to the gate and drain of the 1st FET, thereby writing a current value of the image data current. A preliminary charging circuit is connected to the data line. Before the writing operation in the predetermined time period is expired, a current of a predetermined current value is applied to the image data current so that a gate-source voltage of the 1st FET is equal to or larger than a threshold value.

摘要翻译： 有源矩阵型显示装置包括各自具有电致发光元件EL的多个像素电路，用于控制在EL中流动的电流的第一FET，以及设置在第一FET的栅极与漏极之间的第二FET。 多个像素电路被布置成矩阵并且每列连接到数据线。 第二FET导通预定的时间段，并且流过数据线的图像数据电流被提供给第一FET的栅极和漏极，从而写入图像数据电流的当前值。 预充电电路连接到数据线。 在预定时间段内的写入操作期满之前，将预定电流值的电流施加到图像数据电流，使得第一FET的栅极 - 源极电压等于或大于阈值。

公开(公告)号：US07532207B2

公开(公告)日：2009-05-12

申请号：US10790738

申请日：2004-03-03

申请人： Somei Kawasaki ,  Fujio Kawano ,  Masami Iseki

发明人： Somei Kawasaki ,  Fujio Kawano ,  Masami Iseki

IPC分类号： G09G3/1029

CPC分类号： G09G3/3283 ,  G09G3/006 ,  G09G3/325 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2320/029 ,  G09G2320/043

摘要： For making outputs of a drive circuits accurate, the drive circuit is composed of a plurality of current signal generation circuits for outputting a current signal to each of a plurality of output units, a current signal output line to which outputs of the plurality of current signal generation circuits are commonly connected, a correction value output circuit for outputting a correction value obtained by evaluating the output of one or more specific circuits of the plurality of current signal generation circuits on a basis of current values output through the current signal output line, and a correction circuit for correcting an image signal supplied to the current signal generation circuits by means of the correction value.

摘要翻译： 为了使驱动电路的输出精确，驱动电路由多个电流信号生成电路构成，用于向多个输出单元中的每一个输出电流信号，电流信号输出线，多个电流信号的输出 通常连接发电电路，校正值输出电路，用于输出通过基于通过电流信号输出线输出的电流值来评估多个电流信号发生电路的一个或多个特定电路的输出而获得的校正值，以及 校正电路，用于通过校正值校正提供给当前信号发生电路的图像信号。

公开(公告)号：US20090102853A1

公开(公告)日：2009-04-23

申请号：US12063306

申请日：2007-03-30

申请人： Somei Kawasaki ,  Masami Iseki ,  Fujio Kawano

发明人： Somei Kawasaki ,  Masami Iseki ,  Fujio Kawano

IPC分类号： G09G5/02 ,  H04N5/66

CPC分类号： G09G3/3241 ,  G09G3/3275 ,  G09G2300/0408 ,  G09G2310/0262 ,  G09G2310/027 ,  G09G2310/0297

摘要： A color display apparatus which has a color display unit in which color pixels are arranged in a matrix, a plurality of data lines, and a plurality of column drive circuits which output data signals to a plurality of data lines for every row, has a first dispersion circuit for selecting column drive circuits used as output destinations of analog video signals for every color which are obtained by DA converting digital video signals for every color, a second dispersion circuit for selecting data lines used as output destinations of the data signals from the column drive circuits, and control circuits which control the first and second dispersion circuits so as to sequentially change the drive circuits used as the output destinations of the analog video signals for each color, and the data lines used as the output destinations of the data signals, for every scanning period.

摘要翻译： 一种彩色显示装置，其具有彩色像素排列成矩阵的彩色显示单元，多条数据线以及将数据信号输出到每行的多条数据线的多列列驱动电路，具有第一 用于选择列驱动电路的色散电路，其用作通过DA转换每种颜色的数字视频信号而获得的每种颜色的模拟视频信号的输出目的地;第二色散电路，用于从列中选择用作数据信号的输出目的地的数据线 驱动电路和控制电路，其控制第一和第二色散电路，以便依次改变用作每种颜色的模拟视频信号的输出目的地的驱动电路，以及用作数据信号的输出目的地的数据线， 在每个扫描期间。

公开(公告)号：US20060120357A1

公开(公告)日：2006-06-08

申请号：US11290578

申请日：2005-12-01

申请人： Somei Kawasaki ,  Masami Iseki ,  Fujio Kawano ,  Takanori Yamashita

发明人： Somei Kawasaki ,  Masami Iseki ,  Fujio Kawano ,  Takanori Yamashita

IPC分类号： H04L12/66

CPC分类号： G09G3/3283 ,  G09G3/325 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2320/0233

摘要： Even if characteristics of transistors differ every circuit, in order to suppress an influence by the different characteristics and stabilize the programming operation to a control electrode of a drive transistor even if a data signal is small, there is provided a programming apparatus for programming signals which are supplied to a circuit array (61, 62) having a plurality of circuits each having transistors (M11, M12), first switching elements (M21, M22) connected to control electrodes of the transistors, and second switching elements (M31, M32) each connected to one main electrode of each of the transistors. The programming apparatus has: a current generating circuit (M3, M4) which is connected in common to each of the second switching elements of the circuit array and generates a current corresponding to a current flowing in the transistor of the selected circuit; and an operational amplifier (OPAMP1) which is connected in common to each of the first switching elements of the circuit array and supplies the program signal to the control electrode of the transistor of the selected circuit. A data signal and a signal corresponding to the current generated by the current generating circuit are inputted to the operational amplifier.

摘要翻译： 即使每个电路的晶体管的特性不同，为了抑制不同特性的影响，即使数据信号较小，也能将编程操作稳定在驱动晶体管的控制电极上，因此提供了一种用于对信号进行编程的编程装置 被提供给具有多个电路的电路阵列（61,62），每个电路各自具有晶体管（M 11，M 12），连接到晶体管的控制电极的第一开关元件（M 21，M 22）和第二开关元件 M 31，M 32），每个连接到每个晶体管的一个主电极。 编程装置具有：电流产生电路（M 3，M 4），其共同连接到电路阵列的每个第二开关元件，并产生与流过所选电路的晶体管的电流相对应的电流; 以及与电路阵列的每个第一开关元件共同连接的运算放大器（运算放大器1），并将编程信号提供给所选电路的晶体管的控制电极。 将数据信号和与电流产生电路产生的电流对应的信号输入到运算放大器。

公开(公告)号：US08072542B2

公开(公告)日：2011-12-06

申请号：US11693291

申请日：2007-03-29

申请人： Masami Iseki ,  Somei Kawasaki ,  Fujio Kawano

发明人： Masami Iseki ,  Somei Kawasaki ,  Fujio Kawano

IPC分类号： H03L7/00

CPC分类号： H04N5/23293 ,  G09G3/006 ,  G09G3/3241 ,  G09G3/3283 ,  G09G2320/0233 ,  G09G2320/029 ,  H04N5/14

摘要： A correction sampling signal generation circuit is disposed subsequent to a plural-stage sampling signal generation circuit for sequentially generating sampling signals in response to an input timing signal, an extended sampling circuit is disposed subsequent to a plural-stage sampling circuit for sampling a video signal at timing of the sampling signal, and a data signal is sampled at timing of the sampling signal generated by the extended sampling circuit. In a timing adjustment period, the data signal for adjustment is generated, the phases of the data signal and the timing signal are relatively shifted, the outputs of the sampling circuits are supplied to a common output line through respective switches, and the phase of the optimum timing signal or the video signal is determined based on the output from the common output line.

摘要翻译： 校正采样信号发生电路设置在多级采样信号产生电路之后，用于响应于输入定时信号顺序产生采样信号，扩展采样电路设置在用于对视频信号进行采样的多级采样电路之后 在采样信号的定时，并且在由扩展采样电路产生的采样信号的定时对数据信号进行采样。 在定时调整期间，产生用于调整的数据信号，数据信号和定时信号的相位相对偏移，采样电路的输出通过各个开关提供给公共输出线，并且相位 基于公共输出线的输出确定最佳定时信号或视频信号。

公开(公告)号：US20050122150A1

公开(公告)日：2005-06-09

申请号：US10994310

申请日：2004-11-23

申请人： Masami Iseki ,  Somei Kawasaki ,  Fujio Kawano ,  Takanori Yamashita

发明人： Masami Iseki ,  Somei Kawasaki ,  Fujio Kawano ,  Takanori Yamashita

IPC分类号： G09G3/30 ,  G09F9/30 ,  G09G3/20 ,  G09G3/32 ,  H03K5/153

CPC分类号： G09G3/3283 ,  G09G3/3241 ,  G09G3/325 ,  G09G3/3266 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0289 ,  G09G2330/021 ,  G09G2330/026 ,  G09G2330/045

摘要： The present application discloses a driver having a configuration comprising: a drive transistor for supplying a current of the quantity corresponding to a gate potential, into the element as a driving current; a first switch installed in the path of the driving current passing between the element and the drive transistor, for controlling the flow of the driving current; a second switch for switching between the first state of setting the gate potential of the drive transistor and the second state of keeping the set gate potential; a circuit for supplying a signal for controlling the flow of the driving current in a restricted state to the first switch, for a predetermined period in a period after the starting the supply of the potential for driving the drive transistor from a power source and until start of driving the element in a normal operation; a circuit for supplying a signal for setting the second switch at the first state, to the second switch: and a circuit for interrupting a signal for setting the gate potential while the second switch is in the first state in the predetermined period.

摘要翻译： 本申请公开了一种驱动器，其具有如下结构：驱动晶体管，用于将与栅极电位相对应的量的电流作为驱动电流提供到元件中; 安装在通过元件和驱动晶体管之间的驱动电流的路径中的第一开关，用于控制驱动电流的流动; 第二开关，用于在设置驱动晶体管的栅极电位的第一状态和保持所设置的栅极电位的第二状态之间切换; 在开始从电源驱动驱动晶体管的电位开始到起动之间的期间内，将预定时间段提供用于将限制状态下的驱动电流的流动控制到第一开关的电路 在正常操作中驱动元件; 用于向第二开关提供用于将第二开关设置的信号的电路提供给第二开关;以及用于在第二开关处于预定周期中处于第一状态时中断用于设置栅极电位的信号的电路。

公开(公告)号：US08154539B2

公开(公告)日：2012-04-10

申请号：US12042459

申请日：2008-03-05

申请人： Somei Kawasaki ,  Fujio Kawano ,  Masami Iseki

发明人： Somei Kawasaki ,  Fujio Kawano ,  Masami Iseki

IPC分类号： G09G5/00 ,  G06F3/038

CPC分类号： G09G3/3283 ,  G09G3/006 ,  G09G3/325 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2320/029 ,  G09G2320/043

摘要： For making outputs of a drive circuits accurate, the drive circuit is composed of a plurality of current signal generation circuits for outputting a current signal to each of a plurality of output units, a current signal output line to which outputs of the plurality of current signal generation circuits are commonly connected, a correction value output circuit for outputting a correction value obtained by evaluating the output of one or more specific circuits of the plurality of current signal generation circuits on a basis of current values output through the current signal output line, and a correction circuit for correcting an image signal supplied to the current signal generation circuits by means of the correction value.

公开(公告)号：US20060132395A1

公开(公告)日：2006-06-22

申请号：US11275011

申请日：2005-12-01

申请人： Somei Kawasaki ,  Masami Iseki ,  Fujio Kawano ,  Takanori Yamashita

发明人： Somei Kawasaki ,  Masami Iseki ,  Fujio Kawano ,  Takanori Yamashita

IPC分类号： G09G3/22

CPC分类号： G09G3/3283 ,  G09G3/325 ,  G09G2300/0426 ,  G09G2300/0861 ,  G09G2310/0251 ,  G09G2320/0223

摘要： A current programming apparatus having two data lines for a pixel line is presented. An image data current is supplied to the first and the second data lines alternatively by switching M1 and M2 complementally. By switching M7 and M8 on during the switches M1 and M2 turn on respectively, a constant current is supplied to the data line to which the data current is not supplied. The scanning signals are applied so as to write a constant current into pixels immediately before the data current is written. Thus a write-in defect by a fluctuation in the threshold voltages is prevented.

摘要翻译： 提出了一种具有用于像素线的两条数据线的当前编程设备。 通过互补地切换M 1和M 2，将图像数据电流交替地提供给第一和第二数据线。 通过在开关M 1和M 2分别导通时切换M 7和M 8导通，向不提供数据电流的数据线提供恒定电流。 施加扫描信号，以便在写入数据电流之前将恒定电流写入像素。 因此，防止了由阈值电压的波动引起的写入缺陷。

公开(公告)号：US20060061403A1

公开(公告)日：2006-03-23

申请号：US11219730

申请日：2005-09-07

申请人： Somei Kawasaki ,  Fujio Kawano ,  Masami Iseki

发明人： Somei Kawasaki ,  Fujio Kawano ,  Masami Iseki

IPC分类号： H03L5/00

CPC分类号： G09G3/3233 ,  G09G3/3241 ,  G09G3/325 ,  G09G3/3283 ,  G09G3/3291 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/066 ,  G09G2320/0238 ,  G09G2320/0252 ,  G09G2320/0276 ,  G09G2320/043 ,  G09G2330/021 ,  H03K3/356113 ,  H03K3/356165 ,  H03K19/018571

摘要： A first current mirror circuit performs its normal operation when a first switch is turned on, and is constructed so that a period during which the first current mirror circuit can output a current is realized when the first switch is turned off. A second current mirror circuit is connected to the first current mirror circuit so that the output current of the first current mirror circuit is decreased by an output current of the second current mirror circuit. A current output of a transistor and a current output of the first current mirror circuit are connected and outputted as an output signal. The first switch and a second switch are controlled by the output signal or a signal formed by the output signal being passed through a buffer circuit.