公开(公告)号：US09178592B1

公开(公告)日：2015-11-03

申请号：US14340004

申请日：2014-07-24

Applicant: Silicon Laboratories Inc.

Inventor： Younes Djadi ,  Russell Croman ,  Russell Schultz ,  Scott T. Haban

IPC: H03B1/02 ,  H04B7/06 ,  H04B1/00

CPC classification number: H04B7/08 ,  H04B1/0007 ,  H04B1/40 ,  H04B7/06

Abstract: Systems and methods are disclosed that implement multiple inter-chip (IC) links to communicate digital signals and data between multiple tuner circuit chips of a radio frequency (RF) antenna diversity system. The multiple IC communication links may be employed, for example, to simultaneously communicate different signals and/or data between individual tuner circuit chips of a multi-signal type antenna diversity system in an asynchronous manner, and may be employed to achieve simultaneous antenna diversity for multiple RF signal types using a scalable IC communication link architecture that includes multiple IC communication links to interconnect a varying number of RF tuner circuit chips.

Abstract translation: 公开了实现多个芯片间（IC）链路以在射频（RF）天线分集系统的多个调谐器电路芯片之间传送数字信号和数据的系统和方法。 可以采用多个IC通信链路，例如，以异步方式同时在多信号型天线分集系统的各个调谐器电路芯片之间传送不同的信号和/或数据，并且可以用于实现同时的天线分集 使用包括多个IC通信链路以便互连多个RF调谐器电路芯片的可扩展IC通信链路架构的多个RF信号类型。

公开(公告)号：US09042499B2

公开(公告)日：2015-05-26

申请号：US14062958

申请日：2013-10-25

Applicant: Silicon Laboratories Inc.

Inventor： Michael R. May ,  Scott T. Haban

IPC: H03D1/04 ,  H03D1/06 ,  H03K5/01 ,  H03K6/04 ,  H04B1/10 ,  H04L1/00 ,  H04L25/08 ,  H04B1/12

CPC classification number: H04B1/12 ,  H04B15/06 ,  H04B2215/067

Abstract: Radio frequency (RF) receivers having whitened digital clocks and related methods are disclosed. Disclosed embodiments generate whitened clocks having random variations that are used to operate digital processing blocks so that interference created by the whitened clocks is seen as white noise within the received RF signal spectrum. RF input signals are received by RF front-ends (RFFEs) that output analog signals associated with channels within the RF input signals. These analog signals are converted to digital information and processed by digital receive path circuitry that outputs digital data associated with the channel. The digital receive path circuitry includes a whitened clock generator that generates a whitened clock having random variations and which a digital processing block that operates based upon the whitened clock. Further, the RFFE and the digital receive path circuitry are located within a single integrated circuit.

Abstract translation: 公开了具有白化数字时钟和相关方法的射频（RF）接收机。 公开的实施例产生具有用于操作数字处理块的随机变化的白化时钟，使得由白化时钟产生的干扰在接收的RF信号频谱内被视为白噪声。 RF输入信号由RF前端（RFFE）接收，RF前端输出与RF输入信号内的信道相关的模拟信号。 这些模拟信号被转换成数字信息并由数字接收路径电路进行处理，该电路输出与该信道相关联的数字数据。 数字接收路径电路包括白化时钟发生器，其产生具有随机变化的白化时钟，以及基于白化时钟操作的数字处理块。 此外，RFFE和数字接收路径电路位于单个集成电路内。

公开(公告)号：US20150117573A1

公开(公告)日：2015-04-30

申请号：US14062958

申请日：2013-10-25

Applicant: Silicon Laboratories Inc.

Inventor： Michael R. May ,  Scott T. Haban

IPC: H04B1/12

CPC classification number: H04B1/12 ,  H04B15/06 ,  H04B2215/067

Abstract: Radio frequency (RF) receivers having whitened digital clocks and related methods are disclosed. Disclosed embodiments generate whitened clocks having random variations that are used to operate digital processing blocks so that interference created by the whitened clocks is seen as white noise within the received RF signal spectrum. RF input signals are received by RF front-ends (RFFEs) that output analog signals associated with channels within the RF input signals. These analog signals are converted to digital information and processed by digital receive path circuitry that outputs digital data associated with the channel. The digital receive path circuitry includes a whitened clock generator that generates a whitened clock having random variations and which a digital processing block that operates based upon the whitened clock. Further, the RFFE and the digital receive path circuitry are located within a single integrated circuit.

Abstract translation: 公开了具有白化数字时钟和相关方法的射频（RF）接收机。 公开的实施例产生具有用于操作数字处理块的随机变化的白化时钟，使得由白化时钟产生的干扰在接收的RF信号频谱内被视为白噪声。 RF输入信号由RF前端（RFFE）接收，RF前端输出与RF输入信号内的信道相关的模拟信号。 这些模拟信号被转换成数字信息并由数字接收路径电路进行处理，该电路输出与该信道相关联的数字数据。 数字接收路径电路包括白化时钟发生器，其产生具有随机变化的白化时钟，以及基于白化时钟操作的数字处理块。 此外，RFFE和数字接收路径电路位于单个集成电路内。