公开(公告)号：US4636823A

公开(公告)日：1987-01-13

申请号：US617495

申请日：1984-06-05

申请人： Shlomo Margalit ,  Amnon Yariv ,  Zeev Rav-Noy

发明人： Shlomo Margalit ,  Amnon Yariv ,  Zeev Rav-Noy

IPC分类号： H01L29/10 ,  H01L29/812 ,  H01L29/78

CPC分类号： H01L29/8122 ,  H01L29/1029

摘要： High transconductance vertical FETs are produced in III-V epitaxially grown layers doped n, p and n, with the in-between submicron (0.15 .mu.m) layer serving as the FET channel. The layer on the drain side of the channel may be thicker (3 .mu.m) than on the source side (1.5 .mu.m). The structure is V-grooved to expose a nearly vertical surface that is Si implanted or regrown with graded n-type GaAs/GaAlAs before a gate contact is deposited on the vertical structure. An alternative to employ a heterostructure with GaAlAs layers for the source and drain, and GaAs for the channel layer. Graded GaAs/GaAlAs is then selectively regrown in the channel layer.

摘要翻译： 在掺杂n，p和n的III-V外延生长层中产生高跨导垂直FET，其中亚微米（0.15μm）层用作FET沟道。 通道的漏极侧的层可以比源极侧（1.5μm）更厚（3μm）。 该结构是V沟槽的，以在栅极接触沉积在垂直结构上之前露出被注入或再分散有n型GaAs / GaAlAs的Si的几乎垂直的表面。 采用GaAlAs层用于源极和漏极的异质结构的替代方案，以及用于沟道层的GaAs。 然后在沟道层中选择性地再析出分级的GaAs / GaAlAs。