公开(公告)号：US11903299B2

公开(公告)日：2024-02-13

申请号：US17292973

申请日：2018-11-16

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Takao Saitoh ,  Masahiko Miwa ,  Masaki Yamanaka ,  Yi Sun ,  Yohsuke Kanzaki ,  Seiji Kaneko

IPC: H01L29/08 ,  H10K59/88 ,  H10K50/844 ,  H10K59/124

CPC classification number: H10K59/88 ,  H10K50/844 ,  H10K59/124

Abstract: A TEG near the perimeter of a frame region is away from a TFT, which is disposed in a display region and is actually used for screen display. Hence, the characteristics of the TEG can change in a manner different from that in the characteristics of the TFT within the display region. Accordingly, provided is a display device that includes a TEG pattern disposed between the display region and a trench, and includes a dummy pixel circuit disposed between the display region and a barrier wall. The TEG pattern is outside the display region and is adjacent to at least the dummy pixel circuit.

公开(公告)号：US11681388B2

公开(公告)日：2023-06-20

申请号：US17603305

申请日：2019-04-19

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Masaki Yamanaka ,  Yi Sun ,  Takao Saitoh ,  Masahiko Miwa ,  Yohsuke Kanzaki

IPC: G06F3/041 ,  G06F3/044 ,  H10K50/84 ,  H10K59/40 ,  H10K59/131

CPC classification number: G06F3/0412 ,  G06F3/0445 ,  G06F3/0446 ,  H10K50/841 ,  H10K59/131 ,  H10K59/40 ,  G06F2203/04107

Abstract: A display device includes a plurality of upper layer electrodes including a first upper layer electrode and a second upper layer electrode electrically separated from the first upper layer electrode, and a lower layer electrode provided in common with the first upper layer electrode and a second upper layer electrode and overlapping with the first upper layer electrode and the second upper layer electrode via an insulating film. The first upper layer electrode includes a first protrusion protruding toward the second upper layer electrode, and the second upper layer electrode includes a second protrusion protruding toward the first upper layer electrode. The lower layer electrode is provided with a wide portion having a width greater than those of the first protrusion and the second protrusion, the wide portion overlapping at least with a gap between the first protrusion and the second protrusion.

公开(公告)号：US11508760B2

公开(公告)日：2022-11-22

申请号：US16980172

申请日：2018-03-15

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Masahiko Miwa ,  Yohsuke Kanzaki ,  Takao Saitoh ,  Masaki Yamanaka ,  Yi Sun ,  Seiji Kaneko

IPC: H01L27/32 ,  H01L27/12

Abstract: An active matrix substrate includes a plurality of first contact holes extending through an inorganic insulating film, a first protection layer that is a silicon nitride film, and a second protection layer, a plurality of second contact holes extending through the inorganic insulating film and the second protection layer, a first transistor, and a second transistor. A channel region of the second transistor does not overlap the first protection layer.

公开(公告)号：US10256346B2

公开(公告)日：2019-04-09

申请号：US15516434

申请日：2015-10-01

Applicant: Sharp Kabushiki Kaisha

Inventor： Takao Saitoh ,  Yohsuke Kanzaki ,  Yutaka Takamaru ,  Keisuke Ide ,  Seiji Kaneko

IPC: H01L29/786 ,  H01L27/12 ,  C23C16/42

Abstract: In a semiconductor device including a semiconductor layer made of an oxide semiconductor, occurrence of variance in the characteristics of TFTs is suppressed. In a manufacturing process of a semiconductor device (100) where a passivation film (17) is to be formed at an upper layer of a semiconductor layer (11) made of an oxide semiconductor, deposition conditions of the passivation film (17) are set such that the proportion of pure metal (the ratio of pure metal to all the components of the semiconductor layer (11)) at an interface of the semiconductor layer (11) to the passivation film (17) becomes higher than the proportion of pure metal in the bulk of the semiconductor layer (11).

公开(公告)号：US09690155B2

公开(公告)日：2017-06-27

申请号：US15304114

申请日：2015-04-09

Applicant: Sharp Kabushiki Kaisha

Inventor： Yutaka Takamaru ,  Seiji Kaneko ,  Takao Saitoh ,  Yohsuke Kanzaki ,  Keisuke Ide ,  Hiroshi Matsukizono

IPC: G02F1/1362 ,  G02F1/1333 ,  G02F1/1368 ,  G02F1/1343

CPC classification number: G02F1/136227 ,  G02F1/133345 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/1362 ,  G02F1/1368

Abstract: A TFT substrate (100A) of a liquid crystal display panel includes: an organic interlayer insulating layer (24) covering a TFT; a first transparent electrically-conductive layer (25) provided in the first region of a surface of the organic interlayer insulating layer (24); and an inorganic dielectric layer (26) covering the first transparent electrically-conductive layer (25) and provided in a second region of the surface of the organic interlayer insulating layer (24) which is different from the first region, the inorganic dielectric layer (26) containing SiN, wherein an arithmetic mean roughness Ra of the first region and the second region of the surface of the organic interlayer insulating layer (24) is not less than 3.45 nm and not more than 5.20 nm.

公开(公告)号：US12041820B2

公开(公告)日：2024-07-16

申请号：US17273287

申请日：2018-09-06

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Takao Saitoh ,  Masahiko Miwa ,  Yohsuke Kanzaki ,  Yi Sun ,  Masaki Yamanaka ,  Seiji Kaneko

IPC: H10K59/121 ,  H10K71/00 ,  H10K59/12

CPC classification number: H10K59/1213 ,  H10K71/00 ,  H10K59/1201

Abstract: In a method for manufacturing an active matrix substrate, forming of an underlayer inorganic insulating film includes applying a resist onto the underlayer inorganic insulating film, performing an ashing process of forming a surface having irregularities on a surface of the resist by a first ashing process, and, after the ashing process has been performed, roughening a surface of the underlayer inorganic insulating film by performing a second ashing process and an etching process on the underlayer inorganic insulating film. When forming a semiconductor film, a surface of at least a part of the semiconductor film is roughened following a rough surface of the underlayer inorganic insulating film.

公开(公告)号：US11659746B2

公开(公告)日：2023-05-23

申请号：US16979453

申请日：2018-03-09

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Takao Saitoh ,  Seiji Kaneko ,  Yohsuke Kanzaki ,  Masahiko Miwa ,  Masaki Yamanaka ,  Yi Sun

IPC: H10K59/131 ,  H10K59/124 ,  H10K77/10 ,  H10K102/00

CPC classification number: H10K59/131 ,  H10K59/124 ,  H10K77/111 ,  H10K2102/311

Abstract: A first wiring line and a second wiring line are extended to an upper face of a resin substrate exposed from a slit formed in at least one layer of an inorganic insulating film, a first flattening film is provided within the slit which exposes the upper face of the resin substrate between the portions to which the first wiring line and the second wiring line are extended, and the first wiring line and the second wiring line are electrically connected to each other via a third wiring line provided between an end face of the first flattening film and the upper face of the resin substrate.

公开(公告)号：US11416108B2

公开(公告)日：2022-08-16

申请号：US17258442

申请日：2018-07-25

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Masaki Yamanaka ,  Yi Sun ,  Masahiko Miwa ,  Takao Saitoh ,  Yohsuke Kanzaki ,  Seiji Kaneko

IPC: G06F3/047 ,  G06F3/041 ,  H01L27/32 ,  H01L51/52 ,  H01L51/56

Abstract: A display device includes a display area and a frame area surrounding the display area. The display device comprises a TFT layer, a light-emitting element layer, a sealing layer including a first inorganic sealing film, an organic sealing film, and a second inorganic sealing film, a bank coated with the first inorganic sealing film and the second inorganic sealing film, a touch panel function layer, and a plurality of touch panel wires running to intersect with the bank in planar view and connected to the touch panel function layer. The second inorganic sealing film includes a bank coating that coats an upper face of the bank, and a protrusion, in a clearance between neighboring two of the plurality of touch panel wires, protrudes from the bank coating toward the display area or away from the display area.

公开(公告)号：US10510781B2

公开(公告)日：2019-12-17

申请号：US16078249

申请日：2017-02-21

Applicant: Sharp Kabushiki Kaisha

Inventor： Kazuatsu Ito ,  Seiji Kaneko ,  Yohsuke Kanzaki ,  Takao Saitoh ,  Makoto Nakazawa

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/51 ,  H01L29/786 ,  G02F1/1368

Abstract: A method of producing a semiconductor device according to an embodiment of the present invention includes: step (C) of forming an oxide semiconductor layer of a plurality of thin film transistors on a gate dielectric layer; step (F) of forming an aperture in an interlevel dielectric layer, the aperture being located between an active region and a plurality of terminal portions and extending through the interlevel dielectric layer; and step (G) of, after step (F), forming an upper conductive portion on the interlevel dielectric layer. In step (C), a protection layer made of the same oxide semiconductor film as the oxide semiconductor layer is formed above a region of the gate dielectric layer that is located between the active region and the plurality of terminal portions. In step (F), the aperture is formed so as to overlap the protection layer.

公开(公告)号：US10355040B2

公开(公告)日：2019-07-16

申请号：US15770742

申请日：2017-02-22

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Kazuatsu Ito ,  Seiji Kaneko ,  Yohsuke Kanzaki ,  Takao Saitoh ,  Tadayoshi Miyamoto

IPC: H01L31/10 ,  H01L27/146 ,  H01L29/786 ,  H01L31/105

Abstract: An off-leakage current of a photodiode is reduced in a photoelectric conversion device. A photoelectric conversion device (100) includes: an oxide semiconductor layer (5) provided on a substrate (1); a passivation film (6) and a planarizing film (7) which are stacked on the oxide semiconductor layer; and a photodiode (9) including a lower electrode (91), a photoelectric conversion layer (92), and an upper electrode (93). The lower electrode is connected to a source electrode (4) via a contact hole provided in the passivation film and the planarizing film. No photoelectric conversion layer is provided directly above the contact hole.