公开(公告)号：US5291139A

公开(公告)日：1994-03-01

申请号：US683245

申请日：1991-04-10

Applicant: Serge Fruhauf ,  Francois Tailliet

Inventor： Serge Fruhauf ,  Francois Tailliet

IPC: G11C17/14 ,  G11C16/06 ,  G11C17/16 ,  G11C17/18 ,  G11C29/04 ,  H01H85/055 ,  H01H85/30 ,  H01H85/46 ,  G01R31/02 ,  G01R17/00 ,  G01R31/28

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: A circuit for the detection of a fuse with oxide vertical fusing has another fuse that is of the same type but cannot be blown and, in parallel with each of the fuses, a voltage reference circuit. The output of each of the voltage reference circuits is an input of a differential comparator. This differential comparator is preferably provided with a voltage reference circuit that is independent of the supply voltage Vcc.

Abstract translation: 用于检测具有氧化物垂直熔断器的保险丝的电路具有另一个具有相同类型但不能被熔断的熔丝，并且与每个保险丝并联一个电压参考电路。 每个电压参考电路的输出是差分比较器的输入。 该差分比较器优选地设置有独立于电源电压Vcc的电压参考电路。

公开(公告)号：US09001602B2

公开(公告)日：2015-04-07

申请号：US13610443

申请日：2012-09-11

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/06

CPC classification number: G11C29/02 ,  G11C29/06

Abstract: A method for testing an integrated circuit includes, in a burn-in test mode, two steps during which gate oxides of conductive high voltage MOS transistors of the integrated circuit are subjected to a first test voltage, and blocked high voltage MOS transistors of the integrated circuit are subjected to a second test voltage. The first test voltage is set to a value higher than a high supply voltage supplied to the high voltage MOS transistors in a normal operating mode, to make the gate oxides of transistors considered as insufficiently robust break down. The second test voltage is set to a value lower than the first test voltage and which can be supported by the blocked transistors, the states of the transistors being changed between the two steps.

Abstract translation: 集成电路的测试方法包括在老化测试模式中，集成电路的导电高压MOS晶体管的栅极氧化物经受第一测试电压的两个步骤，并且集成的高压MOS晶体管被阻塞 电路经受第二测试电压。 将第一测试电压设置为高于在正常工作模式下提供给高电压MOS晶体管的高电源电压的值，以使晶体管的栅极氧化物被认为不足够强大地分解。 第二测试电压被设置为低于第一测试电压并且可被阻塞晶体管支持的值，晶体管的状态在两个步骤之间改变。

公开(公告)号：US20120256180A1

公开(公告)日：2012-10-11

申请号：US13443778

申请日：2012-04-10

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: H01L23/58 ,  H01L21/66

CPC classification number: H01L22/34

Abstract: Embodiments of the disclosure relate to a method of evaluating a semiconductor wafer dicing process, comprising providing evaluation lines extending in at least one scribe line of the wafer, dicing the wafer in the scribe line, evaluating the length of the evaluation lines, providing an information about their length, and using the information to evaluate the dicing process.

Abstract translation: 本公开的实施例涉及一种评估半导体晶片切割工艺的方法，包括提供在晶片的至少一个划线中延伸的评估线，在划线中切割晶片，评估评估线的长度，提供信息 关于他们的长度，并使用信息来评估切片过程。

公开(公告)号：US20080061810A1

公开(公告)日：2008-03-13

申请号：US11844627

申请日：2007-08-24

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: G01R31/02 ,  G01R31/28

CPC classification number: G01R31/3187 ,  G01R31/2831 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/31717 ,  G01R31/318511

Abstract: A method for testing an integrated circuit is provided comprising steps of providing at least one first conductive path stretching along an element of the integrated circuit, applying a voltage at a point of the first conductive path, performing a first measurement of the voltage at a point of the first conductive path, and determining whether the integrated circuit is damaged according to the result of the first measurement. Application to the detection of damage due to the sawing or electrical testing of integrated circuits.

Abstract translation: 提供一种用于测试集成电路的方法，包括以下步骤：提供沿着集成电路的元件拉伸的至少一个第一导电路径，在第一导电路径的点处施加电压，在一点处执行电压的第一测量 的第一导电路径，并且根据第一测量的结果确定集成电路是否损坏。 应用于检测集成电路锯切或电气测试造成的损坏。

公开(公告)号：US5347185A

公开(公告)日：1994-09-13

申请号：US892941

申请日：1992-06-03

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: H01L27/02 ,  H01P1/22 ,  H03K3/26

CPC classification number: H01L27/0251

Abstract: A CMOS circuit protected against latch-up. A limiter parallel to the internal circuitry of the CMOS circuit increases the external current for the triggering of the latch-up in the event of overvoltage on the supply. In one embodiment, the parallel limiter is intrinsically protected against electrostatic discharges. In another embodiment, the limiter is protected by a series connected resistor and a separate shunt-connected ESD protection structure.

Abstract translation: CMOS电路防止闭锁。 与CMOS电路的内部电路并联的限幅器会增加外部电流，以便在电源过压时触发闩锁。 在一个实施例中，并联限制器被固有地防止静电放电。 在另一个实施例中，限幅器由串联连接的电阻器和独立的分流连接的ESD保护结构保护。

公开(公告)号：US4890187A

公开(公告)日：1989-12-26

申请号：US264202

申请日：1988-10-28

Applicant: Francois Tailliet ,  Jacek Kowalski

Inventor： Francois Tailliet ,  Jacek Kowalski

IPC: H01L23/60 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/78 ,  H01L29/866

CPC classification number: H01L27/0251

Abstract: To protect integrated circuits as efficiently as possible against electrostatic discharges, by putting a diode in avalanche mode without untimely triggering of this avalance mode by overvoltages of non-electrostatic origin, the following solution is proposed: through an insulated gate surrounding the cathode of the diode, the threshold for transition into avalanche mode of the diode is modified according to the slope of the overvoltages appearing at the terminal to be protected. The gate is connected to the terminal by an integrating circuit in such a way that the overvoltages are applied to the gate with a certain delay, inducing a potential difference between the cathode and the gate which is all the greater as the front of the overvoltage is steep. The avalanche triggering threshold is higher in the latter case than in the former one, and it is thus distinguish between overvoltages of diverse origins.

Abstract translation: 为了尽可能高效地保护集成电路免受静电放电，通过将二极管置于雪崩模式，而不会因非静电原点的过电压而不及时地触发此平衡模式，提出了以下解决方案：通过围绕二极管阴极的绝缘栅极 根据出现在要保护的端子处的过电压的斜率来修改二极管转变为雪崩模式的阈值。 栅极通过积分电路连接到端子，使得过电压以一定的延迟施加到栅极，引起阴极和栅极之间的电位差，其中过电压的前面是大的 陡。 在后一种情况下，雪崩触发阈值高于前者，因此区分不同来源的过电压。

公开(公告)号：US08310879B2

公开(公告)日：2012-11-13

申请号：US12965152

申请日：2010-12-10

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: An electrically programmable and erasable non-volatile memory point may have at least one floating-gate transistor connected to a bit line and to a ground line, and may be programmed with a programming voltage. In an erase phase of the memory point, a first, negative, voltage may be applied to the bit line and to the ground line. The absolute value of the first voltage may be smaller than a threshold value of a PN diode. A second positive voltage which is smaller than the programming voltage may be applied to the control gate of the floating-gate transistor. The difference between the second voltage and the first voltage may be equal to the programming voltage, and, in a writing phase, the first negative voltage may be applied to the control gate of the floating-gate transistor, and the second voltage may be applied to the bit line.

Abstract translation: 电可编程和可擦除非易失性存储点可以具有连接到位线和接地线的至少一个浮栅晶体管，并且可以用编程电压进行编程。 在存储点的擦除阶段，可以将第一，负电压施加到位线和接地线。 第一电压的绝对值可以小于PN二极管的阈值。 小于编程电压的第二正电压可以被施加到浮栅晶体管的控制栅极。 第二电压和第一电压之间的差可以等于编程电压，并且在写入阶段中，第一负电压可以被施加到浮栅晶体管的控制栅极，并且可以施加第二电压 到位线。

公开(公告)号：US20070204191A1

公开(公告)日：2007-08-30

申请号：US11670553

申请日：2007-02-02

Applicant: Francois Tailliet ,  Laurent Murillo

Inventor： Francois Tailliet ,  Laurent Murillo

IPC: G01R31/28

CPC classification number: G01R31/318392 ,  G01R31/31703 ,  G01R31/31705 ,  G01R31/3177

Abstract: A method for detecting a malfunction in a state machine is described. The state machine has an operation modeled by a set of states linked to each other by transitions, the state machine generating, upon each transition, output signals according to input signals comprising signals generated during a previous transition. During a transition, the method comprises steps of generating at least one control signal according to a control signal generated during a previous transition, determining an expected value of the control signal, and comparing the control signal with the expected value.

Abstract translation: 描述了一种用于检测状态机故障的方法。 状态机具有由通过转换彼此链接的一组状态建模的操作，状态机根据包括在先前转换期间生成的信号的输入信号在每次转换时产生输出信号。 在转换期间，该方法包括以下步骤：根据在先前转换期间产生的控制信号产生至少一个控制信号，确定控制信号的期望值，以及将控制信号与期望值进行比较。

公开(公告)号：US20070153589A1

公开(公告)日：2007-07-05

申请号：US11610046

申请日：2006-12-13

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: G11C11/34 ,  G11C16/06 ,  G11C7/10 ,  G11C5/14

CPC classification number: H02M3/073 ,  H02M2001/0041

Abstract: A voltage regulation device comprises a voltage regulator for regulating a direct voltage supplied by a voltage generator, the voltage regulator comprising means for stopping or activating the voltage generator depending on whether the voltage to be regulated is greater or lower than a setpoint voltage. The regulation device comprises a voltage limiter having a first threshold voltage greater than the setpoint voltage to clip a transient overvoltage greater than the first threshold voltage, appearing in the voltage to be regulated. Application can be made to the regulation of the high voltage used to program or erase a non-volatile memory.

Abstract translation: 电压调节装置包括用于调节由电压发生器提供的直流电压的电压调节器，该电压调节器包括用于根据被调节电压是否大于或小于设定点电压来停止或激活电压发生器的装置。 调节装置包括具有大于设定点电压的第一阈值电压的电压限制器，用于钳位出现在待调节电压中的大于第一阈值电压的瞬态过电压。 可以应用于对用于编程或擦除非易失性存储器的高电压的调节。

公开(公告)号：US20050062519A1

公开(公告)日：2005-03-24

申请号：US10666540

申请日：2003-09-19

Applicant: Philippe Ganivet ,  Thierry Giovinazzi ,  Francois Tailliet

Inventor： Philippe Ganivet ,  Thierry Giovinazzi ,  Francois Tailliet

IPC: G05F1/10 ,  G05F3/24 ,  H03K3/0231 ,  H03K3/03 ,  H03L7/00

CPC classification number: H03K3/0231 ,  G05F3/242 ,  H03K3/03

Abstract: A time base circuit, for an oscillator and apparatus, defines a time interval in terms of a time taken for a capacitor to charge from a reference voltage level to a detection voltage level. The circuit operates by: supplying at the start of the interval a capacitor charging current, using a first semiconductor device supplied from a first power supply voltage, the device delivering the charging current according to a predetermined dependency on the first power supply voltage; and identifying the detection voltage level to signal the end of the time interval, using a second semiconductor device supplied from the first power supply voltage, the second semiconductor device identifying the detection voltage level value according to the same predetermined dependency on the first power supply voltage as for the first semiconductor device, the time interval being made substantially independent of variations of the first power supply voltage.

Abstract translation: 用于振荡器和装置的时基电路根据电容器从参考电压电平到检测电压电平充电所花费的时间来定义时间间隔。 电路的工作原理是：使用从第一电源电压提供的第一半导体器件，在间隔开始时提供电容器充电电流，该装置根据对第一电源电压的预定依赖性传送充电电流; 以及使用从所述第一电源电压提供的第二半导体装置来识别所述检测电压电平以用信号通知所述时间间隔的结束，所述第二半导体器件根据与所述第一电源电压相同的预定依赖性来识别所述检测电压电平值 对于第一半导体器件，时间间隔基本上与第一电源电压的变化无关。