MAGNETIC MEMORY WITH SEPARATE READ AND WRITE PATHS
    1.
    发明申请
    MAGNETIC MEMORY WITH SEPARATE READ AND WRITE PATHS 有权
    具有独立阅读和写入功能的磁记录

    公开(公告)号:US20140015075A1

    公开(公告)日:2014-01-16

    申请号:US13966361

    申请日:2013-08-14

    IPC分类号: H01L43/02

    摘要: Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction.

    摘要翻译: 公开了具有分离的读和写路径的磁存储器。 磁存储器单元包括具有第一磁化取向的第一端部,具有第二磁化取向的相对的第二端部和第一端部与第二端部之间的中间部分的铁磁条,所述中间部分具有 自由磁化方向。 第一磁化取向与第二磁化取向相反。 隧道势垒将磁性参考层与形成磁性隧道结的中间部分分开。 位线电耦合到第二端部。 源极线电耦合到第一端部,并且读取线电耦合到磁性隧道结。

    Magnetic memory with separate read and write paths
    4.
    发明授权
    Magnetic memory with separate read and write paths 有权
    具有独立读写路径的磁记忆体

    公开(公告)号:US08681541B2

    公开(公告)日:2014-03-25

    申请号:US13966361

    申请日:2013-08-14

    IPC分类号: G11C11/14

    摘要: Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction.

    摘要翻译: 公开了具有分离的读和写路径的磁存储器。 磁存储器单元包括具有第一磁化取向的第一端部,具有第二磁化取向的相对的第二端部和第一端部与第二端部之间的中间部分的铁磁条,所述中间部分具有 自由磁化方向。 第一磁化取向与第二磁化取向相反。 隧道势垒将磁性参考层与形成磁性隧道结的中间部分分开。 位线电耦合到第二端部。 源极线电耦合到第一端部,并且读取线电耦合到磁性隧道结。

    Floating source line architecture for non-volatile memory
    5.
    发明授权
    Floating source line architecture for non-volatile memory 有权
    用于非易失性存储器的浮动源线架构

    公开(公告)号:US08582347B2

    公开(公告)日:2013-11-12

    申请号:US13751592

    申请日:2013-01-28

    IPC分类号: G11C11/10

    摘要: A method and apparatus for writing data to a non-volatile memory cell, such as an STRAM memory cell or an RRAM memory cell. In some embodiments, a plurality of N non-volatile memory cells, where N is a greater than two, are connected to a common floating source line. A write circuit is adapted to program a selected memory cell of the plurality to a selected data state by passing a write current of selected magnitude through the selected memory cell and concurrently passing a portion of the write current in parallel through each of the remaining N−1 memory cells of the plurality via the common floating source line.

    摘要翻译: 用于将数据写入诸如STRAM存储器单元或RRAM存储器单元的非易失性存储单元的方法和装置。 在一些实施例中,其中N大于2的多个N个非易失性存储器单元连接到公共的浮动源线。 写入电路适于通过将所选择的大小的写入电流通过所选择的存储器单元来编程所选择的数据状态的所选择的存储单元,并且并行地通过所述剩余的N- 1个存储单元经由公共浮动源线。

    Floating Source Line Architecture for Non-Volatile Memory
    6.
    发明申请
    Floating Source Line Architecture for Non-Volatile Memory 有权
    非易失性存储器的浮动源线架构

    公开(公告)号:US20130135922A1

    公开(公告)日:2013-05-30

    申请号:US13751592

    申请日:2013-01-28

    IPC分类号: G11C13/00 G11C11/16

    摘要: A method and apparatus for writing data to a non-volatile memory cell, such as an STRAM memory cell or an RRAM memory cell. In some embodiments, a plurality of N non-volatile memory cells, where N is a greater than two, are connected to a common floating source line. A write circuit is adapted to program a selected memory cell of the plurality to a selected data state by passing a write current of selected magnitude through the selected memory cell and concurrently passing a portion of the write current in parallel through each of the remaining N−1 memory cells of the plurality via the common floating source line.

    摘要翻译: 用于将数据写入诸如STRAM存储器单元或RRAM存储器单元的非易失性存储单元的方法和装置。 在一些实施例中,其中N大于2的多个N个非易失性存储器单元连接到公共的浮动源线。 写入电路适于通过将所选择的大小的写入电流通过所选择的存储器单元来编程所选择的数据状态的所选择的存储单元,并且并行地通过所述剩余的N- 1个存储单元经由公共浮动源线。