公开(公告)号：US20120214308A1

公开(公告)日：2012-08-23

申请号：US13230118

申请日：2011-09-12

Applicant: Satoshi INADA ,  Mitsuhiro OMURA ,  Hisataka HAYASHI

Inventor： Satoshi INADA ,  Mitsuhiro OMURA ,  Hisataka HAYASHI

IPC: H01L21/308

CPC classification number: H01L21/32139 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/038 ,  G03F7/039 ,  G03F7/095 ,  H01L21/0273

Abstract: An aspect of the present embodiment, there is provided a method of fabricating a semiconductor device including providing a film to be processed above a semiconductor substrate, providing a negative-type resist and a photo-curable resist in order, pressing a main surface of a template onto the photo-curable resist, the main surface of the template having a concavo-convex pattern with a light shield portion provided on at least a part of a convex portion, irradiating the template with light from a back surface of the template, developing the negative-type resist and the photo-curable resist so as to print the concavo-convex pattern of the template on the negative-type resist and the photo-curable resist, and etching the film to be processed by using the concavo-convex pattern printed on the negative-type resist and the photo-curable resist as a mask.

Abstract translation: 本实施例的一个方面提供一种制造半导体器件的方法，该半导体器件包括在半导体衬底上提供待加工的膜，依次提供负型抗蚀剂和可光固化抗蚀剂， 模板到可光固化抗蚀剂上，模板的主表面具有凹凸图案，具有设置在凸部的至少一部分上的遮光部分，用来自模板背面的光照射模板，显影 负型抗蚀剂和光固化型抗蚀剂，以便在负型抗蚀剂和可光固化抗蚀剂上印刷模板的凹凸图案，并通过使用凹凸图案来蚀刻待处理的薄膜 印刷在负型抗蚀剂和可光固化抗蚀剂上作为掩模。

公开(公告)号：US20110223750A1

公开(公告)日：2011-09-15

申请号：US13043017

申请日：2011-03-08

Applicant: Hisataka HAYASHI ,  Takeshi Kaminatsui ,  Akio Ui

Inventor： Hisataka HAYASHI ,  Takeshi Kaminatsui ,  Akio Ui

IPC: H01L21/265 ,  C23C16/515 ,  H01L21/3065 ,  H01L21/31

CPC classification number: H01L21/31116 ,  H01J37/32091 ,  H01J37/32146 ,  H01L21/3065

Abstract: According to an embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes: arranging a semiconductor substrate on a first electrode out of first and second electrodes arranged to be opposed to each other in a vacuum container; applying negative first pulse voltage and radio-frequency voltage to the first electrode, the negative first pulse voltage being superimposed with the radio-frequency voltage; applying negative second pulse voltage to the second electrode in an off period of the first pulse voltage; and processing the semiconductor substrate or a member on the semiconductor substrate by plasma formed between the first and second electrodes.

Abstract translation: 根据实施例，公开了一种用于制造半导体器件的方法。 该方法包括：在真空容器内布置成彼此相对的第一和第二电极的第一电极上的半导体衬底布置; 对第一电极施加负的第一脉冲电压和射频电压，负的第一脉冲电压与射频电压叠加; 在所述第一脉冲电压的关闭期间，向所述第二电极施加负的第二脉冲电压; 以及通过在第一和第二电极之间形成的等离子体处理半导体衬底或半导体衬底上的构件。

公开(公告)号：US20150162223A1

公开(公告)日：2015-06-11

申请号：US14626277

申请日：2015-02-19

Applicant: Akio UI ,  Hisataka HAYASHI ,  Takeshi KAMINATSUI ,  Shinji HIMORI ,  Norikazu YAMADA ,  Takeshi OHSE ,  Jun ABE

Inventor： Akio UI ,  Hisataka HAYASHI ,  Takeshi KAMINATSUI ,  Shinji HIMORI ,  Norikazu YAMADA ,  Takeshi OHSE ,  Jun ABE

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/3213 ,  H01L21/66 ,  H01L21/3065 ,  H01L21/311

CPC classification number: H01L21/67069 ,  H01J37/32009 ,  H01J37/32027 ,  H01J37/32045 ,  H01J37/32091 ,  H01J37/321 ,  H01J37/32137 ,  H01J37/32532 ,  H01J2237/3341 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/67253 ,  H01L22/14 ,  H01L22/26

Abstract: There are provided a substrate processing apparatus and a substrate processing method realizing an effective reduction of a voltage change of a substrate on an electrode to reduce the variation of incident energy of ions entering the substrate. The substrate processing apparatus includes: a first electrode holding a substrate on a main surface of the first electrode; a second electrode facing the first electrode; a RF power source applying to the first electrode a RF voltage whose frequency is equal to or higher than 40 MHz; and a pulse voltage applying unit applying to the first electrode a pulse voltage decreasing in accordance with a lapse of time, by superimposing the pulse voltage on the RF voltage.

Abstract translation: 提供了一种基板处理装置和基板处理方法，其实现有效地降低电极上的基板的电压变化，以减少进入基板的离子的入射能量的变化。 基板处理装置包括：第一电极，其在第一电极的主表面上保持基板; 面对所述第一电极的第二电极; RF电源，其向所述第一电极施加频率等于或高于40MHz的RF电压; 以及脉冲电压施加单元，通过将所述脉冲电压叠加在所述RF电压上，向所述第一电极施加根据时间的流逝而减小的脉冲电压。

公开(公告)号：US20120034785A1

公开(公告)日：2012-02-09

申请号：US13045818

申请日：2011-03-11

Applicant: Hisataka HAYASHI ,  Yusuke Kasahara ,  Tsubasa Imamura

Inventor： Hisataka HAYASHI ,  Yusuke Kasahara ,  Tsubasa Imamura

IPC: H01L21/306

CPC classification number: H01L21/31116 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: According to one embodiment, a semiconductor device manufacturing method includes collectively etching layers of a multilayered film including silicon layers and silicon oxide films alternately stacked on a semiconductor substrate. The etching gas of the etching contains at least two types of group-VII elements and one of a group-III element, a group-IV element, a group-V element, and a group-VI element, the energy of ions entering the semiconductor substrate when performing the etching is not less than 100 eV, and an addition ratio of the group-III element, the group-IV element, the group-V element, the group-VI element, and the group-VII element to the group-VII element is 0.5 (inclusive) to 3.0 (inclusive).

Abstract translation: 根据一个实施例，半导体器件制造方法包括共同地蚀刻包含交替层叠在半导体衬底上的硅层和氧化硅膜的多层膜的层。 蚀刻蚀刻气体含有至少两种类型的VII族元素和III族元素，IV族元素，V族元素和VI族元素中的一种，离子的能量进入 进行蚀刻时的半导体基板为100eV以上，III族元素，IV族元素，V族元素，VI族元素和VII族元素相对于 Ⅶ族元素为0.5（含）〜3.0（含）以上。

公开(公告)号：US20090194508A1

公开(公告)日：2009-08-06

申请号：US12363070

申请日：2009-01-30

Applicant: Akio UI ,  Naoki TAMAOKI ,  Takashi ICHIKAWA ,  Hisataka HAYASHI ,  Takeshi KAMINATSUI ,  Shinji HIMORI ,  Norikazu YAMADA ,  Takeshi OHSE ,  Jun ABE

Inventor： Akio UI ,  Naoki TAMAOKI ,  Takashi ICHIKAWA ,  Hisataka HAYASHI ,  Takeshi KAMINATSUI ,  Shinji HIMORI ,  Norikazu YAMADA ,  Takeshi OHSE ,  Jun ABE

IPC: B44C1/22 ,  C23F1/08

CPC classification number: H01J37/32027 ,  H01J37/32045 ,  H01J37/32091

Abstract: A substrate plasma processing apparatus includes a substrate holding electrode and a counter electrode which are arranged in a chamber, a high frequency generating device which applies a high frequency of 50 MHZ or higher to the substrate holding electrode, a DC negative pulse generating device which applies a DC negative pulse voltage in a manner of superimposing on the high frequency, and a controller controlling to cause intermittent application of the high frequency and cause intermittent application of the DC negative pulse voltage according to the timing of on or off of the high frequency.

Abstract translation: 衬底等离子体处理装置包括布置在腔室中的衬底保持电极和对电极，向衬底保持电极施加50MHz以上的高频的高频发生装置，应用了DC负脉冲发生装置 以高频重叠的方式设置直流负脉冲电压，以及控制器，根据高频开启或关闭的定时控制高频频率的间歇施加，直流负脉冲电压的间歇施加。