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    Smart read scheme for memory array sensing
    2.
    发明授权
    Smart read scheme for memory array sensing 有权
    用于存储器阵列感测的智能读取方案

    公开(公告)号：US08885428B2

    公开(公告)日：2014-11-11

    申请号：US13773963

    申请日：2013-02-22

    Applicant: Sandisk 3D LLC

    Inventor： Yingchang Chen ,  Jeffrey Koon Yee Lee

    IPC: G11C7/06 ,  G11C13/00 ,  G11C16/26

    CPC classification number: G11C7/06 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C16/26 ,  G11C2013/0054 ,  G11C2013/0057

    Abstract: Methods for reducing variability in bias voltages applied to a plurality of memory cells during a sensing operation caused by IR drops along a word line shared by the plurality of memory cells are described. In some embodiments, IR drops along a shared word line may be reduced by reducing sensing currents associated with memory cells whose state has already been determined during a sensing operation. In one example, once a sense amplifier detects that a memory cell being sensed is in a particular state, then the sense amplifier may disable sensing of the memory cell and discharge a corresponding bit line associated with the memory cell. In some cases, a bit line voltage associated with a memory cell whose state has not already been determined during a first phase of a sensing operation may be increased during a second phase of the sensing operation.

    Abstract translation: 描述了在由多个存储器单元共享的字线的IR下降引起的感测操作期间减小施加到多个存储单元的偏置电压的变化性的方法。 在一些实施例中，可以通过减少与在感测操作期间已经确定其状态的存储器单元相关联的感测电流来减小沿着共享字线的IR降级。 在一个示例中，一旦读出放大器检测到被感测的存储器单元处于特定状态，则读出放大器可以禁止对存储器单元的感测并放电与存储器单元相关联的相应位线。 在一些情况下，在感测操作的第二阶段期间，与在感测操作的第一阶段尚未确定状态的存储器单元相关联的位线电压可能会增加。

    SMART READ SCHEME FOR MEMORY ARRAY SENSING
    4.
    发明申请
    SMART READ SCHEME FOR MEMORY ARRAY SENSING 有权
    用于记忆阵列感测的SMART阅读方案

    公开(公告)号：US20140241090A1

    公开(公告)日：2014-08-28

    申请号：US13773963

    申请日：2013-02-22

    Applicant: SANDISK 3D LLC

    Inventor： Yingchang Chen ,  Jeffrey Koon Yee Lee

    IPC: G11C7/06

    CPC classification number: G11C7/06 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C16/26 ,  G11C2013/0054 ,  G11C2013/0057

    Abstract: Methods for reducing variability in bias voltages applied to a plurality of memory cells during a sensing operation caused by IR drops along a word line shared by the plurality of memory cells are described. In some embodiments, IR drops along a shared word line may be reduced by reducing sensing currents associated with memory cells whose state has already been determined during a sensing operation. In one example, once a sense amplifier detects that a memory cell being sensed is in a particular state, then the sense amplifier may disable sensing of the memory cell and discharge a corresponding bit line associated with the memory cell. In some cases, a bit line voltage associated with a memory cell whose state has not already been determined during a first phase of a sensing operation may be increased during a second phase of the sensing operation.

    Abstract translation: 描述了在由多个存储器单元共享的字线的IR下降引起的感测操作期间减小施加到多个存储单元的偏置电压的变化性的方法。 在一些实施例中，可以通过减少与在感测操作期间已经确定其状态的存储器单元相关联的感测电流来减小沿着共享字线的IR降级。 在一个示例中，一旦读出放大器检测到被感测的存储器单元处于特定状态，则读出放大器可以禁止对存储器单元的感测并放电与存储器单元相关联的相应位线。 在一些情况下，在感测操作的第二阶段期间，与在感测操作的第一阶段尚未确定状态的存储器单元相关联的位线电压可能会增加。

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