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    NEURAL NETWORK DEVICE AND METHOD
    2.
    发明申请
    NEURAL NETWORK DEVICE AND METHOD 审中-公开

    公开(公告)号：US20190138892A1

    公开(公告)日：2019-05-09

    申请号：US16170081

    申请日：2018-10-25

    Applicant: Samsung Electronics Co., Ltd. ,  Postech Academy-Industry Foundation

    Inventor： Sungho KIM ,  Jinseok KIM ,  Yulhwa KIM ,  Jaejoon KIM ,  Dusik PARK

    IPC: G06N3/063 ,  G06N3/04

    Abstract: A method of performing operations on a plurality of inputs and a same kernel using a delay time by using a same processor, and a neural network device thereof are provided, the neural network device includes input data including a first input and a second input, and a processor configured to obtain a first result by performing operations between the first input and a plurality of kernels, to obtain a second result by performing operations between the second input, which is received at a time delayed by a first interval from a time when the first input is received, and the plurality of kernels, and to obtain output data using the first result and the second result. The neural network device may include neuromorphic hardware and may perform convolutional neural network (CNN) mapping.

    TWO-DIMENSIONAL ARRAY-BASED NEUROMORPHIC PROCESSOR AND IMPLEMENTING METHOD
    6.
    发明公开
    TWO-DIMENSIONAL ARRAY-BASED NEUROMORPHIC PROCESSOR AND IMPLEMENTING METHOD 审中-公开

    公开(公告)号：US20230214637A1

    公开(公告)日：2023-07-06

    申请号：US18120137

    申请日：2023-03-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungho KIM ,  Cheheung KIM ,  Jaeho LEE

    IPC: G06N3/063 ,  G06F7/523 ,  G06F7/50

    CPC classification number: G06N3/063 ,  G06F7/523 ,  G06F7/50 ,  G06F2207/4824

    Abstract: A 2D array-based neuromorphic processor includes: axon circuits each being configured to receive a first input corresponding to one bit from among bits indicating n-bit activation; first direction lines extending in a first direction from the axon circuits; second direction lines intersecting the first direction lines; synapse circuits disposed at intersections of the first direction lines and the second direction lines, and each being configured to store a second input corresponding to one bit from among bits indicating an m-bit weight and to output operation values of the first input and the second input; and neuron circuits connected to the first or second direction lines, each of the neuron circuits being configured to receive an operation value output from at least one of the synapse circuits, based on time information assigned individually to the synapse circuits, and to perform an arithmetic operation by using the operation values.

    DISPLAY PANEL AND DISPLAY APPARATUS INCLUDING SAME
    7.
    发明申请
    DISPLAY PANEL AND DISPLAY APPARATUS INCLUDING SAME 有权

    公开(公告)号：US20210302782A1

    公开(公告)日：2021-09-30

    申请号：US17212490

    申请日：2021-03-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD

    Inventor： Sungho CHOI ,  Sungho KIM ,  Jeongphil SEO ,  Junghyun YOON ,  Minnyeong HAN

    IPC: G02F1/1335 ,  G02F1/1333 ,  G02F1/1339

    Abstract: A display panel and a display apparatus are provided. The display panel may include a first glass substrate; a second glass substrate provided in front of the first glass substrate in a first direction; and a color filter layer provided between the second glass substrate and the first glass substrate in the first direction. The color filter layer may include a plurality of color filters and a black matrix surrounding the plurality of color filters. A side edge of the black matrix may extend beyond a side edge of the first glass substrate in a second direction that is orthogonal to the first direction. The display apparatus may include a backlight unit and the display panel.

    TWO-DIMENSIONAL ARRAY-BASED NEUROMORPHIC PROCESSOR AND IMPLEMENTING METHOD
    8.
    发明申请
    TWO-DIMENSIONAL ARRAY-BASED NEUROMORPHIC PROCESSOR AND IMPLEMENTING METHOD 审中-公开

    公开(公告)号：US20200074284A1

    公开(公告)日：2020-03-05

    申请号：US16274547

    申请日：2019-02-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungho KIM ,  Cheheung KIM ,  Jaeho LEE

    IPC: G06N3/063 ,  G06F7/50 ,  G06F7/523

    Abstract: A 2D array-based neuromorphic processor includes: axon circuits each being configured to receive a first input corresponding to one bit from among bits indicating n-bit activation; first direction lines extending in a first direction from the axon circuits; second direction lines intersecting the first direction lines; synapse circuits disposed at intersections of the first direction lines and the second direction lines, and each being configured to store a second input corresponding to one bit from among bits indicating an m-bit weight and to output operation values of the first input and the second input; and neuron circuits connected to the second direction lines, each of the neuron circuits being configured to receive an operation value output from at least one of the synapse circuits, based on time information assigned individually to the synapse circuits, and to perform a multi-bit operation by using the operation values and the time information.

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