System device, and method for memory interface including reconfigurable channel

    公开(公告)号:US11556279B2

    公开(公告)日:2023-01-17

    申请号:US17209790

    申请日:2021-03-23

    Inventor: Youngwook Kim

    Abstract: A method of communicating with a memory device through a plurality of sub-channels and a control sub-channel includes; setting a first mode or a second mode. In the first mode, writing or reading first data corresponding to a command synchronized to the control sub-channel through the plurality of sub-channels, and in the second mode, independently writing or reading second data and third data respectively corresponding to different commands synchronized to the control sub-channel through the plurality of sub-channels.

    STORAGE DEVICE COMMUNICATING WITH SPECIFIC PATTERN AND OPERATING METHOD THEREOF
    2.
    发明申请
    STORAGE DEVICE COMMUNICATING WITH SPECIFIC PATTERN AND OPERATING METHOD THEREOF 审中-公开
    存储设备与特定模式通信及其操作方法

    公开(公告)号:US20160239220A1

    公开(公告)日:2016-08-18

    申请号:US14994168

    申请日:2016-01-13

    Abstract: A storage device includes a memory device configured to store data and a memory controller connected to the memory device through a data strobe line and a plurality of data lines. The storage device adds a predetermined specific pattern in front of data and processes data input following the specific pattern as valid data during a read or write operation. The specific pattern is provided in alignment with a data strobe signal (DQS) latency cycle. The memory controller detects a specific pattern input from the memory device during a read operation and processes data input following the specific pattern as valid data when the detected specific pattern matches an internally stored specific pattern.

    Abstract translation: 存储装置包括被配置为存储数据的存储器件和通过数据选通线和多条数据线连接到存储器件的存储器控​​制器。 存储装置在数据前面增加预定的特定模式,并且在读取或写入操作期间将跟随特定模式输入的数据作为有效数据进行处理。 提供特定模式与数据选通信号(DQS)延迟周期对齐。 存储器控制器在读取操作期间检测来自存储器件的特定模式输入,并且当检测到的特定模式与内部存储的特定模式匹配时,将特定模式之后的数据输入作为有效数据进行处理。

    Electronic device for performing edge computing service and operation method of electronic device

    公开(公告)号:US12058100B2

    公开(公告)日:2024-08-06

    申请号:US18320688

    申请日:2023-05-19

    CPC classification number: H04L61/4511 H04L61/58

    Abstract: An electronic device and an operation method of an electronic device are provided. The electronic device includes a memory for storing multiple applications including a first application, an edge enabler client (EPC), and multiple domain name system (DNS) caches allocated to each of at least some applications of the multiple applications and/or mapping data obtained by mapping identification information of the at least some applications to the multiple DNS caches; a communication circuit used for a communication connection of an edge service provision server and/or an edge network management server through a base station; and a processor configured to receive, from the first application, an access request for the edge service provision server that the first application desires to access; identify whether a DNS cache corresponding to the first application exits in the multiple DNS caches based on the mapping data and identification information of the first application, acquire an internet protocol (IP) address corresponding to a domain address included in the access request in case that the DNS cache corresponding to the first application exists, and access the edge service provision server based on the acquired IP address and perform the service.

    Storage device for supporting multiple hosts and operation method thereof

    公开(公告)号:US11861238B2

    公开(公告)日:2024-01-02

    申请号:US17852652

    申请日:2022-06-29

    Abstract: An operation method of a storage device including first and second physical functions respectively corresponding to first and second hosts includes receiving performance information from each of the first and second hosts, setting a first weight value corresponding to the first physical function and a second weight value corresponding to the second physical function, based on the received performance information, selecting one of a first submission queue, a second submission queue, a third submission queue, and a fourth submission queue based on an aggregated value table, the first and second submission queues being managed by the first host and the third and fourth submission queues are managed by the second host, processing a command from the selected submission queue, and updating the aggregated value table based on a weight value corresponding to the processed command from among the first and second weights and input/output (I/O) information of the processed command.

    Method and apparatus for data processing based on multicore

    公开(公告)号:US10802885B2

    公开(公告)日:2020-10-13

    申请号:US15982633

    申请日:2018-05-17

    Abstract: A communication technique for combining a fifth generation (5G) communication system that supports higher data transmission rates after fourth generation (4G) systems with Internet of things (IoT) technology and to the system therefor are provided. The disclosure relates to a multiple cores-based data processing method and apparatus, the method including determining whether a condition for a first packet flow among one or more packet flows for data communication is met, if the condition is met, selecting cores to distribute packets of the first packet flow from among the multiple cores, allocating packets received through the first packet flow to the selected cores, and operating the selected cores in parallel to process the packets allocated from the first packet flow.

    Storage device communicating with specific pattern and operating method thereof

    公开(公告)号:US10095420B2

    公开(公告)日:2018-10-09

    申请号:US14994168

    申请日:2016-01-13

    Abstract: A storage device includes a memory device configured to store data and a memory controller connected to the memory device through a data strobe line and a plurality of data lines. The storage device adds a predetermined specific pattern in front of data and processes data input following the specific pattern as valid data during a read or write operation. The specific pattern is provided in alignment with a data strobe signal (DQS) latency cycle. The memory controller detects a specific pattern input from the memory device during a read operation and processes data input following the specific pattern as valid data when the detected specific pattern matches an internally stored specific pattern.

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