公开(公告)号：US20150143048A1

公开(公告)日：2015-05-21

申请号：US14604832

申请日：2015-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoi Jin Lee ,  Young Min Shin

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F1/3234 ,  G06F1/3275 ,  G06F12/0833 ,  G06F12/084 ,  G06F2212/1028 ,  G06F2212/283 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache; and a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, wherein the first cache is configured from a shared portion of the second cache.

Abstract translation: 一种多CPU数据处理系统，包括：多CPU处理器，包括：第一CPU，配置有至少第一内核，第一高速缓存和配置为访问第一高速缓存的第一高速缓存控制器; 以及配置有至少第二核心的第二CPU和被配置为访问第二高速缓存的第二高速缓存控制器，其中所述第一高速缓存由所述第二高速缓存的共享部分配置。

公开(公告)号：US20180336816A1

公开(公告)日：2018-11-22

申请号：US15917073

申请日：2018-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Min Shin ,  Yong-Hun KIM ,  Yeonwoo JUNG

IPC: G09G3/32 ,  H04N5/202

Abstract: A display driver circuit includes a comparator that is configured to compare first pixel data of a plurality of pixel data with second pixel data of the plurality of pixel data, the plurality of pixel data respectively corresponding to a plurality of pixels connected to a data line, a pre-emphasis controller configured to calculate an offset based on a compare result of the comparator and gamma segment points, which are adjacent to the second pixel data, from among a plurality of gamma segment points used as a reference for dividing the plurality of pixel data, a calculator configured to calculate pre-emphasis pixel data based on the second pixel data and the offset, and an output circuit configured to transmit a pre-emphasis gray scale voltage corresponding to the pre-emphasis pixel data and a target gray scale voltage corresponding to the second pixel data to a display panel through the data line.

公开(公告)号：US09817759B2

公开(公告)日：2017-11-14

申请号：US14340215

申请日：2014-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Min Shin

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/084

CPC classification number: G06F12/0811 ,  G06F12/084 ,  G06F2212/1024 ,  G06F2212/601 ,  G06F2212/6042

Abstract: A multi-core CPU system includes a shared L2 cache, an access control logic circuit, a plurality of cores, each core configured to access the shared L2 cache through the access control logic circuit, and a size adjusting circuit configured to adjust a size of the shared L2 cache in response to an indication signal that indicates a number of operation cores among the plurality of cores.

公开(公告)号：US09606920B2

公开(公告)日：2017-03-28

申请号：US14604832

申请日：2015-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoi Jin Lee ,  Young Min Shin

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/084 ,  G06F1/32 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F1/3234 ,  G06F1/3275 ,  G06F12/0833 ,  G06F12/084 ,  G06F2212/1028 ,  G06F2212/283 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache; and a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, wherein the first cache is configured from a shared portion of the second cache.