公开(公告)号：US20180006219A1

公开(公告)日：2018-01-04

申请号：US15414911

申请日：2017-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hun SEO ,  Jung-Ik OH ,  Yoo-Chul KONG ,  Woo-Ram KIM ,  Jong-Chul PARK ,  Gwang-Hyun BAEK ,  Bok-Yeon WON ,  Hye-Jin CHOI

IPC: H01L45/00 ,  H01L27/24 ,  H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L45/1675 ,  H01L27/222 ,  H01L27/2427 ,  H01L27/2463 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: In method of manufacturing a semiconductor memory device, a selection layer and a variable resistance layer may be sequentially formed on a substrate. A preliminary first mask extending in a first direction may be formed on the variable resistance layer. An upper mask extending in a second direction crossing the first direction may be formed on the variable resistance layer and the preliminary first mask. The preliminary first mask may be etched using the upper mask as an etching mask to form a first mask having a pillar shape. The variable resistance layer and the selection layer may be anisotropically etched using the first mask as an etching mask to form a pattern structure including a variable resistance pattern and selection pattern sequentially stacked. The pattern structure may have a pillar shape. Damages to the pattern structure may decrease.