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    SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING THE SAME
    2.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING THE SAME 有权

    公开(公告)号：US20220206062A1

    公开(公告)日：2022-06-30

    申请号：US17471763

    申请日：2021-09-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunhye Oh ,  Hyochul Shin ,  Jinwoo Park ,  Sungno Lee ,  Younghyo Park ,  Yongki Lee ,  Heejune Lee ,  Youngjae Cho ,  Michael Choi

    IPC: G01R31/28 ,  H03M1/12 ,  H03K5/24

    Abstract: A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.

    Integrated circuit performing authentication using challenge-response protocol and method of using the integrated circuit
    3.
    发明授权
    Integrated circuit performing authentication using challenge-response protocol and method of using the integrated circuit 有权

    公开(公告)号：US11368319B2

    公开(公告)日：2022-06-21

    申请号：US17015554

    申请日：2020-09-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yongsoo Kim ,  Juyeon Lee ,  Mijung Noh ,  Yongki Lee ,  Yunhyeok Choi

    IPC: H04L9/32 ,  H04L9/08 ,  G06F21/44 ,  G06F21/73

    Abstract: The present disclosure relates to an integrated circuit and a method of using the integrated circuit used to perform authentication using a challenge-response method. The challenge-response method includes an internal challenge generator, a physically unclonable function (PUF) block, and a response generator. The internal challenge generator is configured to receive a challenge, generate a plurality of internal challenges corresponding to the challenge, and generate at least one valid internal challenge among the plurality of internal challenges using screen information. The physically unclonable function (PUF) block is configured to generate a plurality of valid internal responses respectively changing according to the plurality of valid internal challenges. The response generator is configured to output a response generated using the plurality of valid internal responses.

    INTEGRATED CIRCUIT PERFORMING AUTHENTICATION USING CHALLENGE-RESPONSE PROTOCOL AND METHOD OF USING THE INTEGRATED CIRCUIT
    4.
    发明申请
    INTEGRATED CIRCUIT PERFORMING AUTHENTICATION USING CHALLENGE-RESPONSE PROTOCOL AND METHOD OF USING THE INTEGRATED CIRCUIT 有权

    公开(公告)号：US20210234709A1

    公开(公告)日：2021-07-29

    申请号：US17015554

    申请日：2020-09-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YONGSOO KIM ,  Juyeon Lee ,  Mijung Noh ,  Yongki Lee ,  Yunhyeok Choi

    IPC: H04L9/32 ,  H04L9/08 ,  G06F21/73 ,  G06F21/44

    Abstract: The present disclosure relates to an integrated circuit and a method of using the integrated circuit used to perform authentication using a challenge-response method. The challenge-response method includes an internal challenge generator, a physically unclonable function (PUF) block, and a response generator. The internal challenge generator is configured to receive a challenge, generate a plurality of internal challenges corresponding to the challenge, and generate at least one valid internal challenge among the plurality of internal challenges using screen information. The physically unclonable function (PUF) block is configured to generate a plurality of valid internal responses respectively changing according to the plurality of valid internal challenges. The response generator is configured to output a response generated using the plurality of valid internal responses.

    DEVICE AND METHOD FOR PROVIDING PHYSICALLY UNCLONABLE FUNCTION WITH HIGH RELIABILITY
    5.
    发明公开
    DEVICE AND METHOD FOR PROVIDING PHYSICALLY UNCLONABLE FUNCTION WITH HIGH RELIABILITY 审中-公开

    公开(公告)号：US20240201256A1

    公开(公告)日：2024-06-20

    申请号：US18538692

    申请日：2023-12-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sumin Noh ,  Yongki Lee ,  Jieun Park ,  Yunhyeok Choi ,  Bohdan Karpinskyy

    IPC: G01R31/3177 ,  H04L9/32

    CPC classification number: G01R31/3177 ,  H04L9/3278

    Abstract: A device is provided. The device includes: a plurality of physically unclonable function (PUF) cells, each of the plurality of PUF cells including at least one logic gate and being configured to generate an output signal based on at least one threshold level of the at least one logic gate; a signal generator configured to generate an input signal that is provided to each of the plurality of PUF cells; and a controller configured to, in a test mode, generate a control signal to control the signal generator to vary the input signal to control the plurality of PUF cells to output a plurality of output signals according to the input signal, and identify at least one weak PUF cell from among the plurality of PUF cells based on the output signal generated by the at least one weak PUF cell being an unstable output signal. The controller is further configured to disconnect the plurality of PUF cells from the signal generator in a normal mode.

    APPARATUS AND METHODS FOR DETECTING INVASIVE ATTACKS WITHIN INTEGRATED CIRCUITS
    8.
    发明申请
    APPARATUS AND METHODS FOR DETECTING INVASIVE ATTACKS WITHIN INTEGRATED CIRCUITS 有权

    公开(公告)号：US20210216626A1

    公开(公告)日：2021-07-15

    申请号：US17003313

    申请日：2020-08-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Bohdan Karpinskyy ,  Mijung Noh ,  Jieun Park ,  Yongki Lee ,  Juyeon Lee

    IPC: G06F21/55 ,  G06F7/58 ,  H03K3/84

    Abstract: An apparatus includes an integrated circuit and a plurality of conducting wires disposed on the integrated circuit. The integrated circuit includes: (i) a signal generation circuit, which is configured to generate random signal and selection signal based on random or pseudo-random numbers, (ii) a transmitting circuit configured to select at least one from among the plurality of conducting wires based on the selection signal and to output the random signal through the at least one conducting wire, and (iii) a receiving circuit configured to detect an invasive attack on the integrated circuit based on signal received through the at least one conducting wire.

    ENCRYPTION DEVICE AND OPERATING METHOD OF ENCRYPTION DEVICE
    9.
    发明公开
    ENCRYPTION DEVICE AND OPERATING METHOD OF ENCRYPTION DEVICE 审中-公开

    公开(公告)号：US20240356726A1

    公开(公告)日：2024-10-24

    申请号：US18634211

    申请日：2024-04-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Gapkyoung Kim ,  Jaehyeok Kim ,  Yongki Lee ,  Hongmook Choi

    IPC: H04L9/06

    CPC classification number: H04L9/0631

    Abstract: An encryption device includes an encryption core circuit configured to generate output data by performing an encryption operation on input data, and an encryption controller circuit configured to control an operation of the encryption core. The encryption core circuit includes a shiftrow circuit configured to generate shift data by performing a shiftrow operation on the input data, a security circuit configured to generate permutation data by performing a permutation operation including a mixcolumn multiplication operation on the shift data, a mixcolumn addition circuit configured to generate first mid data by performing a mixcolumn addition operation on the permutation data, and a round key addition operation circuit configured to generate the output data by performing a round key addition operation on the first mid data.

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