公开(公告)号：US20220293205A1

公开(公告)日：2022-09-15

申请号：US17467861

申请日：2021-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUNHYE OH ,  JAEHYEOK KIM ,  YONG KI LEE ,  GAPKYOUNG KIM ,  TAEWOOK PARK

IPC: G11C29/42 ,  G11C29/36 ,  G11C29/10 ,  G11C29/44

Abstract: A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.

公开(公告)号：US20210304751A1

公开(公告)日：2021-09-30

申请号：US17130401

申请日：2020-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNG-NO LEE ,  HYOCHUL SHIN ,  HYUNGDONG ROH ,  YONG KI LEE

IPC: G10L15/22 ,  G10L15/28 ,  G10L15/10 ,  H04R3/00

Abstract: Disclosed is an electronic device which includes an audio processing block for voice recognition in a low-power mode. The electronic device includes a digital microphone that receives a voice signal from a user and converts the received voice signal into a PDM signal, and a DMIC interface circuit. The DMIC interface circuit includes a PDM-PCM converting block that converts the PDM signal into a PCM signal, a maxscale gain tuning block that tunes a maxscale gain of the PCM signal received from the PDM-PCM converting block based on a distance information indicating a physical distance between the user and the electronic device acquired in advance of the converting of the PDM signal, and an anti-aliasing block that performs filtering for acquiring voice data of a target frequency band associated with a PCM signal output from the maxscale gain tuning block.

公开(公告)号：US20150277855A1

公开(公告)日：2015-10-01

申请号：US14672656

申请日：2015-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGHOON SHIN ,  SUN-SOO SHIN ,  KYOUNGMOON AHN ,  YONG KI LEE

IPC: G06F7/523

CPC classification number: G06F7/728 ,  G06F7/5338

Abstract: A Montgomery multiplier includes a partial product computing unit for multiplying a multiplicand and a multiplier; a modulus reduction computing unit for performing a multiplication of a modulus and a quotient that reflects a quotient sign; an accumulation unit for accumulating in a intermediate value an output value of the partial product computing unit and an output value of the modulus reduction computing unit from a previous cycle; a quotient computing unit for receiving an accumulation value of the accumulation unit during a current cycle and calculating a quotient sign to be used during a next cycle; and a quotient sign determination unit for determining a quotient sign to be used during a next cycle from the multiplicand, the multiplier and the quotient.

Abstract translation: 蒙哥马利乘数包括用于乘以被乘数和乘数的部分积计算单元; 模数减少计算单元，用于执行反映商标的模数和商的乘法; 累积单元，用于在中间值中积累所述部分积计算单元的输出值和所述模数减少计算单元的输出值与前一周期; 商计算单元，用于在当前周期期间接收累积单元的累加值，并计算在下一周期期间使用的商标; 以及商符号确定单元，用于确定在被乘数的下一周期期间要使用的商符号，乘数和商。

公开(公告)号：US20190116052A1

公开(公告)日：2019-04-18

申请号：US16140019

申请日：2018-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONGSOO KIM ,  MIJUNG NOH ,  BOHDAN KARPINSKYY ,  KYOUNGMOON AHN ,  YONG KI LEE ,  YUNHYEOK CHOI

IPC: H04L9/32 ,  H04L9/08 ,  H04L9/30 ,  G06F7/58

Abstract: A semiconductor device includes a physical unclonable function (PUF) cell array that includes PUF cells outputting first bits; a non-volatile memory that stores marking bits indicating whether the first bits are valid, first mask bits generated by masking second bits depending on parity of the second bits, and second mask bits generated by masking helper bits of the second bits, the second bits are valid bits from the first bits; an extracting unit that extracts the second bits from the first bits using the marking bits; an unmasking unit that unmasks the second bits using the first mask bits while receiving the second bits to provide the third bits; a bit decoding unit that compresses the third bits to fourth bits while receiving the third bits; and a block decoding unit that generates a security key by decoding the fourth bits and the second mask bits.

公开(公告)号：US20160357515A1

公开(公告)日：2016-12-08

申请号：US15242768

申请日：2016-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONG KI LEE ,  JONGHOON SHIN ,  KyoungMoon AHN ,  Ji-Su KANG ,  Sun-Soo SHIN

IPC: G06F7/72

CPC classification number: G06F7/722 ,  G06F7/728

Abstract: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.