公开(公告)号：US20220293205A1

公开(公告)日：2022-09-15

申请号：US17467861

申请日：2021-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUNHYE OH ,  JAEHYEOK KIM ,  YONG KI LEE ,  GAPKYOUNG KIM ,  TAEWOOK PARK

IPC: G11C29/42 ,  G11C29/36 ,  G11C29/10 ,  G11C29/44

Abstract: A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.